10AS066K2F35E1HG - Arria 10 SX SoC FPGA, 660K LE, 1152-FBGA | Altera
부품 번호: 10AS066K2F35E1HG ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $4250 | $4,250.00 |
| 10 | $3990 | $39,900.00 |
| 50 | $3750 | $187,500.00 |
| 100 | $3520 | $352,000.00 |
| 500 | $3290 | $1,645,000.00 |
10AS066K2F35E1HG 개요
An SoC FPGA is a heterogeneous computing device that combines a general-purpose processor subsystem with programmable logic on a single die, enabling hardware/software co-design for latency-critical and parallel workloads. Within the broader taxonomy, this places the Arria 10 SX under FPGA & CPLD > System on Chip > embedded programmable logic, sitting between traditional microcontrollers (software-only) and discrete FPGAs (logic-only). The Arria 10 family also pioneered 20 nm process technology in mid-range FPGAs, balancing transceiver bandwidth against power.
Key features include 660K logic elements, 1.5 GHz maximum core clock for the HPS, embedded multi-gigabit transceivers supporting protocols such as PCIe Gen3, 10G Ethernet, and CPRI, plus hardened memory controllers, variable-precision DSP blocks, and floating-point hardware assist. Hardened floating-point blocks in the arithmetic logic deliver IEEE 754 single-precision performance critical for DSP pipelines, while dedicated PCI Express Gen3 hard IP blocks save fabric resources.
Typical applications include wireless baseband processing, radar and electronic-warfare signal chains, high-speed serial protocol bridging, broadcast video processing, and medical imaging pre-processing. The -1 speed grade indicates industrial-grade placement, suitable for moderate thermal envelopes and mid-bandwidth SERDES.
When designing with this SoC, ensure the PCB has a 1152-ball FCBGA land pattern with proper microvia stack-up for breakout routing, and provide decoupling per Intel/Altera's pin connection guidelines. For power sequencing, follow the Arria 10 SoC EMIF and HPS power-up sequence in the device family datasheet to avoid in-rush latch-up.
This page synthesizes distributor pricing, drop-in Arria 10 family alternatives, and practical SoC design notes not found in the standalone datasheet PDF.
드롭인 대체품: 10AS066K2F35E1HG — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: 10AS066K2F35E1HG (동일 폼 팩터 및 풋프린트) — 차이점: Package, Logic Elements, Temperature Grade, Mounting Type, RoHS Status.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
10AS066K2F35I1HG
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
10AS066K1F35E1HG
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →10AS066K1F35I1HG
✅ 드롭인✓ 재고 있음
$2275 / 개
데이터시트 보기 →10AS066K2F35E1HG 최대 정격 & 전기적 특성
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 (660K) |
| Hard Processor Subsystem (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | 1.5 GHz |
| 패키지 | 1152-FBGA, FC (35x35 mm) |
| Process Node | 20 nm |
| Speed Grade | -1 (industrial) |
| Temperature Grade | E (extended) |
| Transceivers | Up to 17.4 Gbps (multi-gigabit) |
| DSP Blocks | Variable-precision, hardened floating-point |
| Memory Interfaces | Hardened DDR3/DDR4 controllers |
| PCIe Hard IP | PCI Express Gen3 hard IP blocks |
| RoHS 상태 | Compliant |
| 실장 유형 | Surface Mount (FCBGA) |
| Lead-Free | Yes |
10AS066K2F35E1HG 1152-fbga, fc (35x35 mm) 핀 구성 가이드
10AS066K2F35E1HG(1152-fbga, fc (35x35 mm) 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: 10AS066K2F35E1HG.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
10AS066K2F35E1HG 적합 용도: 6 애플리케이션s: Wireless Baseband Processing, Radar and Electronic Warfare Signal Chains, Broadcast Video Processing, High-Speed Serial Protocol Bridging, Medical Imaging Pre-Processing, Industrial Automation and Vision.
Wireless Baseband Processing
The 10AS066K2F35E1HG fits wireless baseband cards where its 660K logic elements implement channel cards while the dual 1.5 GHz ARM Cortex-A9 MPCore HPS runs the PHY control stack. Placed between antenna interfaces and the backhaul, it provides 24 multi-gigabit transceivers at up to 17.4 Gbps for CPRI or OBSAI fronthaul, plus hardened PCIe Gen3 IP for backhaul. The 17.4 Gbps transceivers and DSP blocks enable LTE/5G NR FFT and FEC offload. Unlike a pure ASIC, the FPGA fabric accelerates protocol upgrades without re-spin.
추천
Radar and Electronic Warfare Signal Chains
The 10AS066K2F35E1HG suits radar receiver/exciter designs where its hardened variable-precision DSP with floating-point assist performs pulse compression and FFT at sustained rates. With 660K LE the device implements multi-channel beamforming, while the dual 1.5 GHz Cortex-A9 HPS handles scheduling and tracking algorithms. The K2 transceiver tier supplies 24 channels of 17.4 Gbps serial link to ADCs/DACs and to neighbouring antenna cards. Its hardened PCIe Gen3 IP streams processed tracks to a host mission computer.
추천
Broadcast Video Processing
The 10AS066K2F35E1HG supports 4K/UHD broadcast pipelines where its 660K LE fabric runs multi-stream HEVC/H.264 encode-decode, color conversion, and graphics overlay in parallel. The dual 1.5 GHz ARM Cortex-A9 HPS hosts a Linux control plane with file ingest and stream management. Its 24 multi-gigabit transceivers provide SDI (SMPTE 2022/2082), HDMI 2.0, and 12G-SDI connectivity. Compared with merchant video SoCs, the FPGA fabric accelerates codec upgrades and custom watermarking without re-spin.
추천
High-Speed Serial Protocol Bridging
The 10AS066K2F35E1HG serves as a multi-protocol bridge converting PCIe Gen3, 10/40 GbE, SATA, and CPRI traffic on a single board. With 24 transceivers at 17.4 Gbps, the device aggregates lanes from multiple physical interfaces and presents a unified logical endpoint. The dual Cortex-A9 HPS at 1.5 GHz handles slow-path control while the 660K LE fabric implements cut-through switching and DMA. Hardened PCIe Gen3 blocks eliminate soft-IP resource overhead and simplify timing closure.
추천
Medical Imaging Pre-Processing
The 10AS066K2F35E1HG accelerates CT, MRI, and ultrasound front-ends where its variable-precision DSP and floating-point blocks perform back-projection, beamforming, and noise filtering in real time. The dual 1.5 GHz Cortex-A9 HPS runs the patient interface and DICOM stack while the 660K LE fabric accelerates the inner imaging loop. Its 17.4 Gbps transceivers connect to high-channel-count ADCs at the probe head. The SoC architecture lets the device replace separate CPU + FPGA + DSP boards.
추천
Industrial Automation and Vision
The 10AS066K2F35E1HG suits factory-automation vision and motion controllers where its dual 1.5 GHz ARM Cortex-A9 HPS runs deterministic EtherCAT or PROFINET masters while the 660K LE fabric accelerates machine-vision pipelines (edge detection, classification, defect inspection). The hardened PCIe Gen3 IP connects to host SCADA systems and 24 transceivers link multi-gigabit camera interfaces. Compared with discrete MCU + GPU stacks, the SoC FPGA reduces BOM, latency, and PCB footprint.
추천
추천 제품 요약
엔지니어링 참조 데이터: 10AS066K2F35E1HG — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | 10AS066K2F35I1HG | 10AS066K1F35E1HG | 10AS066K1F35I1HG |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1152-FBGA, FC (35x35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same |
| Logic Elements | 660K | 660K | 660K | 660K |
| HPS | Dual Cortex-A9 @ 1.5 GHz | Dual Cortex-A9 @ 1.5 GHz | Dual Cortex-A9 @ 1.5 GHz | Dual Cortex-A9 @ 1.5 GHz |
| Transceiver Configuration | K2 (24 channels) | K2 (24 channels) | K1 (12 channels) | K1 (12 channels) |
| Max Transceiver Rate | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps |
| Temperature Grade | E (extended) | I (industrial) | E (extended) | I (industrial) |
| Hardened PCIe Gen3 IP | Yes | Yes | Yes | Yes |
주요 차별점
- K2 transceiver configuration with 24 channels (vs 10AS066K1F35E1HG)
- Extended (E) temperature grade cost optimization (vs 10AS066K2F35I1HG)
- Hardened PCIe Gen3 IP blocks (vs 10AS048H1F34I1HG)
설계 노트
The 1152-FBGA F35 package requires a high-density PCB stack-up with 1-2-1 or 1-2-3-2-1 microvia layers for signal breakout. Use laser-drilled microvias under the BGA balls and standard through-vias on outer breakout layers. Decoupling per Intel/Altera pin connection guidelines: 0.1 uF + 1 uF + 10 uF per power rail as close to the package as possible. Maintain continuous ground return beneath the BGA for signal integrity.
At industrial E grade, the 10AS066K2F35E1HG is rated for junction temperatures up to 100C. Estimated power dissipation at full fabric utilization plus active HPS is typically 15-25 W. Provide a heat spreader or heatsink with at least 4 C/W thermal resistance and ensure PCB inner copper planes are stitched with thermal vias to the top-side spreader. Airflow at 1-2 m/s is recommended in enclosed chassis.
Do not confuse the F35 designator (1152-FBGA) with F34 or F29 packages from other Arria 10 SKUs. The 10AS066K2F35E1HG and 10AS048E2F29I1HG are NOT pin-compatible despite sharing part-number prefix 10AS. Always verify the package code on the Altera ordering part number page before laying out a new PCB or sourcing alternatives.
Differential transceiver channels require length-matched routing within 0.127 mm tolerance to meet 17.4 Gbps eye-mask. Use a 100-ohm differential stack-up with ground reference plane immediately beneath the traces. AC-coupling capacitors must be placed close to the receiver pins and rated for 6 GHz+ bandwidth to avoid attenuating 17.4 Gbps signals.
규정 준수 정보
RoHS and REACH compliant per Altera/Intel product page. Not AEC-Q100 qualified (industrial-grade FPGAs are typically AEC-Q100 only in dedicated auto part numbers).