10AS066K1F35I1HG - Arria 10 SX SoC FPGA, 660K LE, 1.5GHz | Intel
부품 번호: 10AS066K1F35I1HG ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $3250 | $3,250.00 |
| 10 | $3087.5 | $30,875.00 |
| 100 | $2762.5 | $276,250.00 |
| 500 | $2437.5 | $1,218,750.00 |
| 1,000 | $2275 | $2,275,000.00 |
10AS066K1F35I1HG 개요
A SoC FPGA is an integrated circuit that combines a hard processor subsystem (HPS) with programmable FPGA fabric on a single die, enabling hardware/software co-design. The HPS executes control-plane and OS-level workloads while the FPGA fabric accelerates data-plane functions such as signal processing, packet inspection, or custom interfaces; this category sits within the broader embedded processing and programmable-logic taxonomy of field-programmable gate arrays and microprocessors.
Key features of this device include 660K logic elements, embedded DSP blocks for fixed- and floating-point acceleration, hardened memory controllers, multi-gigabit transceivers, and a 1.5 GHz HPS core clock capability. The 1152-ball flip-chip BGA package exposes the maximum logic/memory/peripheral count of the 10AS066 die, targeting high-density applications where board space is less constrained than in smaller FBGA variants.
The architecture combines a TSMC 20 nm process node with Intel's adaptive logic modules (ALMs), 20K (M20K) internal memory blocks, and variable-precision DSP blocks. The hard Cortex-A9 subsystem includes L1/L2 caches, NEON media engines, and a coherent system interconnect to the FPGA fabric for low-latency accelerator hand-off.
Typical applications include 5G wireless baseband prototyping, radar and electronic-warfare signal processing, medical imaging accelerators, broadcast video processing, and high-throughput industrial inspection. The SX device class specifically targets mixed CPU-plus-FPGA workloads.
When designing with this device, pay attention to PCB-level signal integrity on the 35 mm FC-BGA; the flip-chip interconnect demands matched-length routing, controlled impedance, and adequate thermal dissipation through the package substrate. Power planning should leverage the Arria 10 SmartVID feature to minimize dynamic dissipation across PVT corners.
This page synthesizes distributor inventory, lifecycle and pricing data from DigiKey/Mouser/Octopart, same-family Arria 10 SX ordering options, and PCB-level design guidance not duplicated in the manufacturer datasheet.
드롭인 대체품: 10AS066K1F35I1HG — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: 10AS066K1F35I1HG (동일 폼 팩터 및 풋프린트) — 차이점: Logic Elements, Package, Mounting Type, Temperature Grade, Operating Temperature.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
10AS066K1F35E1HG
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →10AS066H1F34I1HG
✅ 드롭인✓ 재고 있음
$3720 / 개
데이터시트 보기 →10AS066H4F34I3SG
✅ 드롭인✓ 재고 있음
$2295 / 개
데이터시트 보기 →10AS057K1F35I1HG
✅ 드롭인✓ 재고 있음
$5210 / 개
데이터시트 보기 →10AS048K1F35I1HG
✅ 드롭인✓ 재고 있음
$3263.87 / 개
데이터시트 보기 →10AS066K1F35I1HG 최대 정격 & 전기적 특성
| MPN | 10AS066K1F35I1HG |
| Manufacturer | Intel (formerly Altera) |
| Series | Arria 10 SX |
| Logic Elements | 660,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Core Clock | 1.5 GHz |
| 패키지 | 1152-FBGA, FC (35x35 mm) |
| Process Node | TSMC 20 nm |
| 실장 유형 | Surface Mount |
| 동작 온도 | -40C to +100C (Industrial) |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
10AS066K1F35I1HG 1152-fbga, fc (35x35 mm) 핀 구성 가이드
10AS066K1F35I1HG(1152-fbga, fc (35x35 mm) 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: 10AS066K1F35I1HG.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
10AS066K1F35I1HG 적합 용도: 6 애플리케이션s: 5G Wireless Baseband Prototyping, Radar and Electronic Warfare Signal Processing, Medical Imaging Accelerators (CT/MRI/Ultrasound), Broadcast Video Processing and IPTV, Industrial Machine Vision and Inspection, Software-Defined Radio and SDR Prototyping.
5G Wireless Baseband Prototyping
The 10AS066K1F35I1HG suits 5G baseband prototyping because it pairs a dual ARM Cortex-A9 hard processor system (1.5 GHz) with 660,000 logic elements of programmable fabric. Engineers typically allocate the HPS to L2/L3 protocol stack and OAM management, while FPGA fabric accelerates FFT, channel estimation, LDPC/turbo decoding and beamforming weight computation. The 20 nm Arria 10 process delivers high DSP throughput at lower power than prior Arria generations. Variable-precision DSP blocks run both fixed- and floating-point operators required by 3GPP NR pipelines. The 1152-FBGA F35 package exposes the maximum transceiver count of the die, supporting CPRI or eCPRI fronthaul links to radio units.
추천
Radar and Electronic Warfare Signal Processing
For radar and electronic-warfare applications, the 10AS066K1F35I1HG's 660K logic elements and variable-precision DSP blocks deliver the arithmetic density required for pulse compression, MTI filtering, and adaptive beamforming across many channels. The dual Cortex-A9 HPS runs tracker and classification software in parallel with FPGA fabric doing front-end FFT pipelines. The industrial temperature range (-40C to +100C) supports airborne and shipboard deployment. Designers leverage hardened memory controllers to feed wide-bandwidth DDR4 sample buffers. Compared to ASICs, this part allows rapid algorithm iteration while sustaining real-time throughput.
추천
Medical Imaging Accelerators (CT/MRI/Ultrasound)
The 10AS066K1F35I1HG fits medical imaging accelerators where real-time reconstruction algorithms (filtered back-projection, iterative reconstruction, beamforming) require both deterministic FPGA pipelines and a control-plane processor for patient I/O. The dual Cortex-A9 subsystem runs the user interface, DICOM stack, and motion-control loops while FPGA fabric handles back-end image reconstruction. The 1152-FBGA F35 package enables the I/O and transceiver bandwidth needed for high-channel-count probe acquisition. Compliance with IEC 60601 patient-safety standards requires careful isolation and firmware validation around this part, but the SoC integration reduces BOM and board area versus a separate MPU plus FPGA architecture.
추천
Broadcast Video Processing and IPTV
In broadcast video systems, the 10AS066K1F35I1HG can act as a high-density video processing engine combining HDMI/SDI ingest, multi-stream transcoding glue logic, and audio/video bridging. The 660K LE fabric supports simultaneous 4K/UHD scaling, frame-rate conversion, and HDR tone-mapping pipelines; the dual Cortex-A9 HPS manages control interfaces (CEC, HDCP, IP-based control). The 1152-ball F35 FC-BGA package provides ample I/O for multiple video interfaces. Arria 10 SmartVID feature minimizes dynamic power dissipation for always-on broadcast head-end chassis, where thermal headroom is constrained.
추천
Industrial Machine Vision and Inspection
For high-throughput machine vision, the 10AS066K1F35I1HG's fabric delivers parallel image-processing pipelines (Sobel, convolution, optical-flow, deep-learning inference) while the dual Cortex-A9 HPS runs the factory control protocol stack (EtherCAT, PROFINET, Modbus TCP). The industrial temperature range supports factory-floor operation. Hardened PCIe Gen2/Gen3 controllers in the HPS enable direct attachment of GigE Vision or CoaXPress frame grabbers. The 1152-FBGA F35 package supplies sufficient I/O for multi-camera aggregation and trigger distribution.
추천
Software-Defined Radio and SDR Prototyping
The 10AS066K1F35I1HG is well suited for software-defined radio prototyping where wide-bandwidth ADC samples feed FPGA fabric running channelizers, demodulators and protocol stacks. The multi-gigabit transceivers exposed by the 1152-ball F35 package support direct ADC/DAC interfaces (JESD204B/C) at rates up to several Gsps. The dual Cortex-A9 HPS hosts a Linux stack running GNU Radio or custom frameworks, while FPGA fabric accelerates physical-layer DSP. Industrial temperature operation and 20 nm low-power process suit both benchtop SDR instruments and deployed tactical radio systems.
추천
추천 제품 요약
엔지니어링 참조 데이터: 10AS066K1F35I1HG — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | 10AS066K1F35E1HG | 10AS066H1F34I1HG | 10AS066H4F34I3SG | 10AS057K1F35I1HG | 10AS048K1F35I1HG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA FC (35x35) | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 570,000 | 480,000 |
| HPS Core Clock | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Temperature Grade | Industrial (-40C to +100C) | Extended | Industrial | Industrial | Industrial | Industrial |
| Speed Grade | K1 | K1 | H1 | H4 | K1 | K1 |
| Process Node | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
주요 차별점
- Highest logic-element density in the 10AS066 family (vs 10AS057K1F35I1HG)
- Industrial temperature grade operation (vs 10AS066K1F35E1HG)
- K1 speed grade (highest in family) (vs 10AS066H1F34I1HG)
설계 노트
The 1152-ball flip-chip FBGA package requires matched-length routing, controlled-impedance stack-up, and via-in-pad escape for high-speed transceiver and DDR traces. Use the Intel Arria 10 pin connection guidelines and Quartus pin planner to confirm PCB padstack matches the 1 mm pitch F35 ball map. Estimated: at 1 mm ball pitch, fanout routing typically needs at least 6 PCB layers with HDI micro-vias; budget for at least 8 layers including ground planes adjacent to each signal layer for return-path continuity.
Estimated: a fully utilized 10AS066 die can dissipate 15-25 W in worst-case workloads. With the FC-FBGA F35 package, attach a heatsink or thermal interface material to the package top, and ensure the PCB has continuous copper beneath the device for bottom-side thermal relief. Use Quartus PowerPlay early in the design cycle to model junction temperature; SmartVID dynamically lowers core voltage to manage power dissipation.
Do not assume pin compatibility across different Arria 10 SX package codes (F35 vs F34 vs F29) without consulting the device pin-out file - the F35 and F34 codes signal different ball maps despite shared 1152-ball FC-BGA form factor. Confirm logic-element count and transceiver count before substituting 10AS057 or 10AS048 die variants, as those reduce DSP/LE resources by 14-27% and may break timing closure.
규정 준수 정보
RoHS compliance and lead-free status confirmed from the Altera/Intel product page. AEC-Q100 not applicable (this is a programmable logic device, not a discrete automotive IC). REACH and halogen-free status not explicitly stated in the verified web data and marked as unknown.
