EP1810JI-35 vs EP1810GC-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JI-35 disebabkan oleh Intel dan EP1810GC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP1810GC-35 EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP1810JI-35 EP1810GC-35
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Masa Terakhir Dibeli
Device Family Classic EPLD —
Macrocells 48 16
Logic Array Blocks 8 LABs of 16 macrocells —
Dedicated Inputs 48 —
Pin-to-Pin Propagation Delay (tPD) 35 ns —
Speed Grade -35 —
Kemasan 28-pin JLCC (J-leaded ceramic, windowed) CPGA-68 (Ceramic Pin Grid Array, 68-pin)
Process Technology CMOS EPROM (UV-erasable) —
Suhu Operasi -40C to +85C (Industrial) [DATA_NEEDED: operating temperature range]
Tegangan Pemberi Arus 5 V (typical classic EPLD) [DATA_NEEDED: VCC range]
Programmability UV-erase, windowed for lab reprogram —
Jenis Pemasangan Through-Hole (J-lead) Through Hole
Status RoHS [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] Not applicable (legacy ceramic package)
Aras MSL [DATA_NEEDED: MSL rating] —
Programming Interface JEDEC fuse file via legacy programmer —
Device Type — EPLD (Erasable Programmable Logic Device)
Logic Family — Altera Classic EPLD
Technology — CMOS, UV-erasable EPROM cells
Bilangan Pin — 68
Propagation Delay (tpd max) — 40 ns
Maximum Inputs — 64
Maximum Outputs — 48
I/O Standard — TTL-compatible
Programming Method — UV erasure + EPROM programming
Lead-Free Status — Not applicable
Manufacturer (current source) — Rochester Electronics (authorized Altera EPLD partner)
Original Manufacturer — Altera Corporation (now Intel FPGA)

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