EP1810JI-35 vs EP1810GC-35 比較
詳細並排比較 EP1810JI-35 由 Intel 與 EP1810GC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JI-35 | EP1810GC-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 16 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| 封裝 | 28-pin JLCC (J-leaded ceramic, windowed) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 工作溫度 | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| 供應電壓 | 5 V (typical classic EPLD) | [DATA_NEEDED: VCC range] |
| Programmability | UV-erase, windowed for lab reprogram | — |
| 安裝類型 | Through-Hole (J-lead) | Through Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | Not applicable (legacy ceramic package) |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| 腳位數 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |