10AX090U1F45I1SG - Arria 10 GX FPGA 900K LE 1932-FCBGA | Intel
MPN: 10AX090U1F45I1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11951.92 | $11,951.92 |
| 10 | $11500 | $115,000.00 |
| 50 | $10800 | $540,000.00 |
| 100 | $10250 | $1,025,000.00 |
| 250 | $9750 | $2,437,500.00 |
Drop-in alternatives for 10AX090U1F45I1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →10AX090U1F45I1SG Maximum Ratings & Electrical Characteristics
| Product Type | FPGA - Field Programmable Gate Array |
| Series | Arria 10 GX |
| Logic Elements | 900,000 LE |
| Adaptive Logic Modules (ALMs) | 339,620 ALM |
| Embedded Memory | 47.32 Mbit |
| Number of I/O | 480 user I/O |
| Number of Terminals | 1932 balls |
| Package / Case | 1932-BBGA, FCBGA |
| Package Code | BGA (Square) |
| Form of Terminal | Ball |
| Mounting Type | Surface Mount |
| Operating Temperature Grade | INDUSTRIAL |
| Process Technology | 20 nm |
| Transceiver Speed | Up to 28.05 Gbps (per Arria 10 GX family) |
| Configuration | JTAG, Passive Serial, Active Serial |
| Hard IP | PCIe Gen3/Gen2 hard IP, variable-precision DSP, PLL |
| Packaging | Tray |
| RoHS Status | Compliant |
10AX090U1F45I1SG bga (square) Pin Configuration Guide
Complete pinout information for 10AX090U1F45I1SG (bga (square) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090U1F45I1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090U1F45I1SG is suitable for 6 applications: 100G/400G Optical Transport Line Card, 5G Baseband and Fronthaul DSP, Military Radar and Electronic Warfare, Medical Imaging Accelerator (CT, MRI, Ultrasound), Broadcast Video Processing and 8K Routing, Data Center Accelerator / Smart NIC.
100G/400G Optical Transport Line Card
The 10AX090U1F45I1SG is well-suited for 100G/400G optical line cards thanks to its 28.05 Gbps-capable transceivers (U1 grade at 14.1 Gbps can drive QSFP28 modules and CFP2/CFP4 DACs via four bonded channels) and 47.32 Mbit of embedded memory for per-channel buffering. Designers typically use the FPGA as the MAC layer between the OTN framer and the optical module, with PCS soft IP and MACsec offload. The 480 user I/O deliver sufficient lane count for 4x100G or 2x400G topologies, while the industrial temperature grade lets the same design ship in both commercial telco and hardened outdoor form factors.
Recommended
5G Baseband and Fronthaul DSP
In 5G fronthaul and baseband applications, the 10AX090U1F45I1SG supports the high DSP throughput required for CPRI/eCPRI bridging, PHY-layer channel coding, and low-latency packet processing. Its 339,620 ALMs and variable-precision DSP blocks deliver the multi-GSPS needed for LDPC/turbo decoders, while the 47.32 Mbit embedded memory provides the buffer depth required for HARQ retransmissions. The hardened PCI Express Gen3 IP allows direct attachment to a baseband SoC across PCIe x8, simplifying board layout versus soft IP approaches.
Recommended
Military Radar and Electronic Warfare
For military radar, SIGINT, and electronic warfare, the 10AX090U1F45I1SG provides the high DSP throughput and ruggedized industrial temperature grade that defense systems demand. The 900K LE and DSP blocks process the wideband digitized returns from ADCs at sample rates up to several GSPS, while the transceiver channels carry raw ADC data into the fabric at 14.1 Gbps (U1) or 28.05 Gbps (U2). System designers often pair the FPGA with a high-channel-count ADC and DAC chain on a VPX or OpenVPX backplane, where the part's high pin count supports multi-board interconnection.
Recommended
Medical Imaging Accelerator (CT, MRI, Ultrasound)
The 10AX090U1F45I1SG accelerates back-end image reconstruction in CT, MRI, and ultrasound systems, where its 47.32 Mbit embedded memory holds the raw sinogram or k-space data while DSP blocks execute filtered back-projection or FFT-based reconstruction. The high ALM count (339,620) is sufficient to implement multiple reconstruction pipelines in parallel, and the PCI Express Gen3 hard IP provides a direct DMA channel to the host processor over a PCIe Gen3 x8 link. Industrial temperature grading lets the same design be reused across diagnostic and mobile ultrasound form factors.
Recommended
Broadcast Video Processing and 8K Routing
In professional broadcast video infrastructure, the 10AX090U1F45I1SG drives 8K/4K routing, multi-format conversion, and SDI-over-IP bridging. Its high-density fabric supports simultaneous processing of up to eight 12G-SDI streams or multiple UHD-SDI/DisplayPort channels, while the transceiver fabric carries SMPTE ST 2110 (IP video) at 25 Gbps per stream. Designers rely on the embedded memory for line buffering and frame store, and on the hardened PCIe for control-plane communication with the broadcast controller.
Recommended
Data Center Accelerator / Smart NIC
For Smart NIC, NVMe-of, and data center accelerator applications, the 10AX090U1F45I1SG provides the PCI Express Gen3 x8 (or Gen4 via soft IP) bandwidth and high-density compute needed for inline crypto, compression, and storage protocol offload. Embedded designers pair the FPGA with DRAM controllers (DDR3/DDR4 soft IP) and 100 GbE MACs running over the transceiver fabric to build an adapter card that offloads host CPU work. The 47.32 Mbit embedded memory provides the on-die cache needed to buffer inline operations.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090U1F45I1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090U1F45E1SG | 10AX090S1F45I1SG | 10AX090S2F45I1SG | 10AX090R2F40I1SG | 10AX090N2F45I1SG | 10AS066K2F35I2SG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1932-BBGA, FCBGA (F45) | 1932-BBGA, FCBGA (F45) | 1932-BBGA, FCBGA (F45) | 1932-BBGA, FCBGA (F45) | 1932-BBGA, FCBGA (F40) | 1932-BBGA, FCBGA (F45) | FBGA-1517 (F35 35 mm) |
| Logic Elements | 900,000 LE | 900,000 LE | 900,000 LE | 900,000 LE | 900,000 LE | 900,000 LE | 660,000 LE |
| Embedded Memory | 47.32 Mbit | 47.32 Mbit | 47.32 Mbit | 47.32 Mbit | 47.32 Mbit | 47.32 Mbit | [DATA_NEEDED] |
| Transceiver Speed | 14.1 Gbps (U1) | 14.1 Gbps (U1) | Up to 12.5 Gbps (S1) | Up to 28.05 Gbps (S2) | Up to 28.05 Gbps (R2) | No transceiver (N) | [DATA_NEEDED] |
| Temperature Grade | INDUSTRIAL (-40C to +100C) | COMMERCIAL (0C to +85C) | INDUSTRIAL | INDUSTRIAL | INDUSTRIAL | INDUSTRIAL | INDUSTRIAL |
| Adaptive Logic Modules (ALMs) | 339,620 ALM | 339,620 ALM | 339,620 ALM | 339,620 ALM | 339,620 ALM | 339,620 ALM | [DATA_NEEDED] |
| User I/O | 480 | 480 | 480 | 480 | [DATA_NEEDED] | 480 | [DATA_NEEDED] |
Key Differentiators
- Industrial temperature grading versus commercial-only alternates (vs 10AX090U1F45E1SG)
- Higher transceiver capability than S-grade but lower cost than U2 (vs 10AX090S1F45I1SG)
- Comparable density at smaller BGA footprint (F40 vs F45) (vs 10AX090R2F40I1SG)
Design Notes
Estimated: At 0.9 V core supply with 900K LE fully utilized and a 14.1 Gbps transceiver fabric at typical toggle activity, the 10AX090U1F45I1SG dissipates in the 15-25 W range. The 1932-FCBGA F45 package requires a thermal interface material (TIM) pad and a heatsink with adequate airflow (>=200 LFM). For rack-mount designs, pair the FPGA with a copper heatspreader plate bonded to the BGA lid. Designers should consult Intel's Arria 10 GX thermal design guide for the recommended PCB land pattern and heat-spreader stack-up. Junction-to-ambient thermal resistance (theta_JA) values are highly package-dependent; verify against the latest device datasheet.
The 1932-ball FCBGA package requires a high-layer-count PCB (typically 12+ layers) to maintain 85 ohm differential and 100 ohm characteristic impedance on the transceiver channels. Use Intel's Arria 10 GX PCB design guidelines for stack-up recommendations, and route transceivers as stripline with continuous reference planes for the first 4 inches. Match differential pair length to within 150 mils and use AC-coupled coupling caps (100 nF) at each end. The BGA ball pitch is fine; escape vias should be micro-vias with staggered or stacked-via topology where possible.
The 10AX090U1F45I1SG requires multiple voltage rails (0.9 V VCC, 1.0 V/1.05 V auxiliary, 1.8 V/3.0 V transceiver supplies, 1.8 V VCCIO). Implement a monotonic power sequencing network with proper rail tracking; Intel specifies Power-On-Reset (POR) sequencing requirements in the device datasheet. Use a multi-rail controller (LTC2974 or similar) with closed-loop margining and current monitoring. Decoupling requires hundreds of low-ESL capacitors distributed beneath the BGA - follow the reference capacitor network in the design guidelines.
For 28.05 Gbps transceiver channels (U2 grade), PCB material selection is critical - use low-loss Megtron-6 or equivalent high-frequency dielectric (Df < 0.005 at 10 GHz) for the signal layers. Channel simulations should target below 1 dB insertion loss per inch at 14 GHz. For 14.1 Gbps (U1), standard FR4 stack-ups with high-grade dielectric are usable but not preferred for production designs. Place the FPGA on a dedicated ground island tied to a chassis ground plane at one point for EMI control.
Do not assume Arria 10 family parts are software-drop-in across all speed grades - Quartus Prime design rules differ between U1 (14.1 Gbps) and U2 (28.05 Gbps) variants. Verify all transceiver IP and timing constraints against the specific speed-grade variant being programmed. For the BGA pinout, never confuse the F45 (45 mm body) with F40 (40 mm body) variants - they are not pin-to-pin compatible even though both are 1932-ball. Confirm the F45 marking on the package before PCB assembly.
Compliance Information
RoHS compliant per verified distributor data. AEC-Q100 is not applicable for FPGAs (it applies to automotive-grade ICs such as analog and discrete semiconductors). Lead-free is standard for Intel FPGAs in this generation. REACH and halogen status not explicitly stated in verified data; marked 'unknown'.
