10AX115H1F34E1SG - Arria 10 GX 1.15M LEs FPGA | Intel | 1152-FCBGA
MPN: 10AX115H1F34E1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3850 | $3,850.00 |
| 10 | $3650 | $36,500.00 |
| 100 | $3380 | $338,000.00 |
| 500 | $3120 | $1,560,000.00 |
| 1,000 | $2895 | $2,895,000.00 |
Drop-in alternatives for 10AX115H1F34E1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX115H2F34E2SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$5500 / Unit
View Datasheet →10AX115H1F34I1SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$6500 / Unit
View Datasheet →10AX115H3F34E3SG
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
10AX115N1F34E1SG
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
10AX115H1F34E1SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory | 68,857,856 bits (68.86 Mbits) |
| User I/Os | 504 |
| Package | 1152-ball FCBGA (F34) |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Transceiver Speed Grade | Up to 17 Gbps (speed grade 1); 24 Gbps supported at higher speed grades |
| Transceiver Count | Up to 24 channels (96 with PMA-only mode, device-family level) |
| PCIe Hard IP | PCIe Gen3 x8 (hardened) |
| DSP Blocks | Variable-precision DSP, ~1,518 to ~1,500 (family-level) |
| PLLs | Fractional and integer PLLs (family-level) |
| Hard Memory Controllers | Yes (DDR3/DDR4/LPDDR3 support) |
| Operating Temperature | Extended (E1) industrial grade |
| RoHS Compliance | Yes (lead-free SG suffix) |
| Mounting Type | Surface Mount, Flip-Chip BGA |
10AX115H1F34E1SG 1152-ball fcbga (f34) Pin Configuration Guide
Complete pinout information for 10AX115H1F34E1SG (1152-ball fcbga (f34) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115H1F34E1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115H1F34E1SG is suitable for 8 applications: 100G Ethernet Aggregation Switch, Radar and Electronic Warfare Signal Processing, Medical Imaging Systems, Test and Measurement Equipment, Broadcast Video Processing, High-Speed Data Acquisition Systems, Aerospace and Defense Signal Processing, PCIe Gen3 Accelerator Card.
100G Ethernet Aggregation Switch
The 10AX115H1F34E1SG's 1,150,000 LEs and 17 Gbps transceivers make it suitable for 100G Ethernet aggregation switching line cards. Multiple 10/25G Ethernet ports can be aggregated through the device's transceiver channels, while the 68.86 Mbits of embedded memory supports packet buffering at line rate. Hardened PCIe Gen3 x8 IP blocks enable direct connection to a switch ASIC or CPU, reducing latency. The F34 1152-ball FCBGA package provides the high pin density required for multi-port SERDES deployments.
Recommended
Radar and Electronic Warfare Signal Processing
The 10AX115H1F34E1SG is well matched to radar and electronic warfare systems requiring high DSP throughput. The device's variable-precision DSP blocks support high-sample-rate FFTs, beamforming, and pulse compression algorithms. The 17 Gbps transceivers enable direct ADC/DAC interface via JESD204B/C, while 504 user I/Os support parallel data capture and timing. Intel's radiation-tolerant Arria 10 variants extend usability to space-grade deployments.
Recommended
Medical Imaging Systems
The 10AX115H1F34E1SG supports medical imaging modalities including ultrasound, CT, and MRI front-end processing. The 1,150,000 LEs enable real-time beamforming in ultrasound systems, while 17 Gbps transceivers connect to high-speed ADCs over JESD204B. The extended temperature grade (E1) and low power-per-LE make the device appropriate for cart-based and portable imaging equipment. PCIe Gen3 x8 hard IP provides direct CPU/GPU interface for downstream image reconstruction.
Recommended
Test and Measurement Equipment
The 10AX115H1F34E1SG is used in high-end test and measurement equipment such as protocol analyzers, high-speed pattern generators, and arbitrary waveform generators. The 504 user I/Os support parallel test bus implementation, while 17 Gbps transceivers handle multi-lane protocol testing (PCIe, USB 3.1, SATA). The 68.86 Mbits of embedded memory stores large pattern sequences and capture buffers, and the device's high Fmax in speed grade 1 enables tight timing margins in measurement applications.
Recommended
Broadcast Video Processing
The 10AX115H1F34E1SG powers broadcast video processing systems including 4K/8K video routers, format converters, and contribution encoders. The 1,150,000 LEs handle multi-channel HEVC/H.265 encoding and decoding, while 17 Gbps transceivers support 12G-SDI and SMPTE ST 2022-7 hitless switching. The 504 user I/Os accommodate large video crosspoint matrices, and PCIe Gen3 x8 hard IP enables direct connection to host media servers.
Recommended
High-Speed Data Acquisition Systems
The 10AX115H1F34E1SG is used in multi-channel high-speed data acquisition systems for scientific instruments, sonar arrays, and high-energy physics experiments. The 17 Gbps transceivers support multi-lane JESD204B/C ADC interfacing, while 1,150,000 LEs handle real-time correlation, FFT, and digital down-conversion. The 68.86 Mbits of embedded memory provides per-channel sample buffering, and the F34 1152-ball FCBGA package supports up to 504 user I/Os for timing, triggering, and control signals.
Recommended
Aerospace and Defense Signal Processing
The 10AX115H1F34E1SG is well suited to aerospace and defense applications including software-defined radio, electronic countermeasures, and secure communications. The 1,150,000 LEs support multi-channel wideband signal processing, while 17 Gbps transceivers enable high-throughput data links. Intel's Arria 10 family offers extended temperature and military temperature grades (E1/I1) for harsh environments. The device's high logic density makes it appropriate for single-board implementations of multi-function RF systems.
Recommended
PCIe Gen3 Accelerator Card
The 10AX115H1F34E1SG serves as a co-processor in PCIe Gen3 accelerator cards for high-performance computing and machine learning inference. The hardened PCIe Gen3 x8 IP block provides direct host interface with low latency, while 1,150,000 LEs handle custom accelerator pipelines. The 17 Gbps transceivers support high-bandwidth memory expansion and external interconnect, and the 504 user I/Os are useful for mezzanine I/O and expansion headers.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115H1F34E1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115H2F34E2SG | 10AX115H1F34I1SG | 10AX115H3F34E3SG | 10AX115N1F34E1SG | 10AX090R2F40E1SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1517-ball FCBGA (F40) - different, requires PCB rework |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 900,000 |
| User I/Os | 504 | 504 | 504 | 504 | 384 | 380 |
| Max Transceiver Data Rate | 17 Gbps (grade 1) | 24 Gbps | 17 Gbps | 17 Gbps | N/A (no transceivers) | 10.3125 Gbps |
| Speed Grade | E1 (extended grade 1) | E2 (extended grade 2) | I1 (industrial grade 1) | E3 (extended grade 3) | E1 (extended grade 1) | E1 (extended grade 1) |
| Embedded Memory | 68.86 Mbits | 68.86 Mbits | 68.86 Mbits | 68.86 Mbits | 68.86 Mbits | 53.2 Mbits |
| PCIe Hard IP | Gen3 x8 | Gen3 x8 | Gen3 x8 | Gen3 x8 | Gen3 x8 | Gen3 x8 |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
Key Differentiators
- Largest logic density in the Arria 10 family (vs 10AX090R2F40E1SG)
- Highest I/O count in the F34 1152-ball package (vs 10AX115N1F34E1SG)
- 17 Gbps transceiver capability at lower cost than speed grade 2 (vs 10AX115H2F34E2SG)
Design Notes
The 10AX115H1F34E1SG can dissipate 25-35W under typical workloads with full transceiver utilization. Per the Intel Arria 10 device datasheet, the F34 FCBGA has a junction-to-ambient thermal resistance of approximately 7-9 C/W with a properly designed thermal solution. Designers must implement a 6-8 layer PCB with internal copper planes (2 oz minimum), an external heat spreader or integrated heatsink, and adequate airflow (200-300 LFM). Early Power Estimator (EPE) should be run during the architecture phase to characterize worst-case power.
At 17 Gbps transceiver rates, signal integrity for the SERDES channels requires careful PCB design. Transceiver channels should use matched-length differential pairs with 100-ohm differential impedance, length matching within 5 mils, and continuous reference planes on adjacent layers. The F34 FCBGA break-out region typically requires 0.8 mm pitch microvia stack-ups and back-drilling for high-speed signals. Use Intel's Transceiver Toolkit and Quartus Prime IBIS-AMI models for channel simulation before tape-out.
The Arria 10 family uses SmartVID for dynamic core voltage scaling, requiring a controller-compliant voltage regulator. Core supply (VCC) operates at 0.85-0.9 V nominal, while transceiver supplies (VCCR/V CCT) and auxiliary supplies (VCCAUX, VCCPLL) require low-noise LDO regulation. Power-on sequence must follow the Arria 10 power management guidelines to avoid latch-up. The E1 speed grade reduces power consumption by approximately 10-15% versus the F1 grade at the same Fmax target.
A common pitfall when migrating between Arria 10 speed grades is the change in transceiver data rate capability - speed grade 1 supports 17 Gbps, while speed grades 2 and 3 are required for 24 Gbps. Designers must not assume higher speed grade functionality in a lower speed grade device. Additionally, the F34 package pinout is shared across all 10AX115 density variants (1,150K LEs), but the F40 and F45 packages have different ball assignments and require separate PCB layouts.
The F34 1152-ball FCBGA has a 1.0 mm ball pitch and 35x35 mm body size, requiring a high-density PCB stack-up. Designers should use an 8-10 layer stack-up with 4-6 routing layers, 0.4-0.5 mm trace width/spacing, and laser-drilled microvias. The 0.9 V core current of a fully populated 10AX115 can exceed 30 A, requiring a multi-rail power distribution network with plane-layer pairs directly above and below the device.
Compliance Information
RoHS and lead-free compliance indicated by SG suffix in the ordering code. AEC-Q100 not applicable (FPGA, not automotive-grade discrete). Conflict minerals compliance per Intel's CMRT filing.
