10AX115N1F40I1SG - Arria 10 GX FPGA 1150K LE | Intel
MPN: 10AX115N1F40I1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4250 | $4,250.00 |
| 10 | $3995 | $39,950.00 |
| 25 | $3850 | $96,250.00 |
| 100 | $3650 | $365,000.00 |
| 250 | $3450 | $862,500.00 |
Drop-in alternatives for 10AX115N1F40I1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX115N1F40E1SG
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View Datasheet →10AX115N1F40I1SG Maximum Ratings & Electrical Characteristics
| Family | Intel Arria 10 GX |
| Device | 10AX115 (10AX115N1F40I1SG) |
| Logic Elements | 1,150,000 |
| Embedded Memory | 68,857,856 bits (68.86 Mbit) |
| User I/O Count | 600 |
| Process Technology | TSMC 20 nm |
| Core Voltage | 0.9 V |
| Transceivers | Integrated multi-gigabit transceivers |
| Hardened PCIe | PCIe Gen3 x8 blocks |
| DSP Blocks | Variable-precision hardened DSP |
| Package | 1517-ball FC-FBGA (F40) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | -40C to +100C (industrial, I suffix) |
| Speed Grade | 1 |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Lifecycle Status | Active |
10AX115N1F40I1SG 1517-ball fc-fbga (f40) Pin Configuration Guide
Complete pinout information for 10AX115N1F40I1SG (1517-ball fc-fbga (f40) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115N1F40I1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115N1F40I1SG is suitable for 7 applications: Wireless Baseband Processing, Broadcast Video Processing, Medical Imaging Acceleration, High-Speed Test & Measurement, Defense Signal Processing, PCIe Gen3 Adapter Cards, Industrial Control & Automation.
Wireless Baseband Processing
The 10AX115N1F40I1SG fits wireless baseband cards thanks to its 1.15M logic elements for LTE/5G NR channelization and FEC, plus hardened multi-gigabit transceivers up to 14.1 Gbps that drive CPRI and JESD204B/C links to RFICs. The PCIe Gen3 x8 blocks enable direct attach to a baseband host processor without an external bridge. Placed on a typical 8-layer FR-4 with a 1.0 mm BGA footprint, the FPGA meets timing closure for 100 MHz baseband clocks with margin.
Recommended
Broadcast Video Processing
For 4K/UHD broadcast video routers and frame synchronizers, the 10AX115N1F40I1SG delivers ample logic density to multiplex SDI, SMPTE 2022, and SMPTE 2110 streams in parallel. The 600 user I/O support up to 150 simultaneous SDI links via transceivers plus parallel GPIO, and 68.86 Mbit embedded memory buffers line/frame stores without external SRAM. Industrial temperature grade suits uncompressed-video truck installations.
Recommended
Medical Imaging Acceleration
The 10AX115N1F40I1SG accelerates CT, MRI, and ultrasound beamforming pipelines using its variable-precision hardened DSP blocks, which deliver up to 1.5 TFLOPs of single-precision throughput at low power. PCIe Gen3 x8 connects to host CPUs at 8 GTPS, while transceivers up to 14.1 Gbps link to high-speed ADCs and DACs. Industrial temperature grade supports clinical and lab environments with stringent EMI compliance.
Recommended
High-Speed Test & Measurement
The 10AX115N1F40I1SG is well suited to high-bandwidth oscilloscopes, logic analyzers, and protocol testers. Its 14.1 Gbps transceivers handle 25G/50G lane aggregation, the 68.86 Mbit embedded memory captures long records without external DRAM, and 600 user I/O fan out to multi-channel probe heads. The hardened PCIe block streams data to host PCs at line rate. Industrial temperature grade handles bench and rack environments.
Recommended
Defense Signal Processing
For radar, SIGINT, and electronic-warfare subsystems, the 10AX115N1F40I1SG provides sufficient logic density for beamforming and FFT pipelines, hardened PCIe for sensor fusion with VPX or SOSA-aligned host cards, and multi-gigabit transceivers for ADC/DAC and optical fiber links. Industrial temperature grade suits ground-mobile and sheltered installations. Designers typically pair the FPGA with high-bandwidth external DDR4 memory for large capture windows.
Recommended
PCIe Gen3 Adapter Cards
PCIe Gen3 x8 accelerator cards use the 10AX115N1F40I1SG as the central compute element. The hardened PCIe block delivers full 8 GTPS throughput with deterministic latency, freeing ALMs for application logic. The 600 user I/O provide flexible GPIO for mezzanine expansion (VITA 57.1 FMC), while transceivers drive high-speed SERDES to daughter cards. Industrial temperature supports server-room and edge deployments.
Recommended
Industrial Control & Automation
The 10AX115N1F40I1SG fits programmable logic controllers and real-time industrial Ethernet gateways. The hardened PCIe block interfaces to industrial PCs, transceivers drive multi-gigabit EtherCAT, PROFINET, or TSN links, and 600 user I/O handle parallel encoder and digital-IO channels. Industrial -40C to +100C operation covers factory-floor deployments, while the 20 nm process keeps dynamic power low for fanless enclosures.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115N1F40I1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115N1F40E1SG | 10AX115H2F34I2SG | 10AX115H2F34I2LG | 10AX115H2F34I1SG | 10AX115H1F34I1SG | 10AX115H2F34E2SG |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1517-ball FC-FBGA (F40) | 1517-ball FC-FBGA (F40) - same | 1517-ball FC-FBGA (F34) | 1517-ball FC-FBGA (F34) | 1517-ball FC-FBGA (F34) | 1517-ball FC-FBGA (F34) | 1517-ball FC-FBGA (F34) |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Embedded Memory | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits | 68,857,856 bits |
| User I/O | 600 | 600 | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] |
| Speed Grade | 1 | 1 | 2 | 2 | 1 | 1 | 2 |
| Temperature Grade | Industrial -40C to +100C | Extended -40C to +125C | Industrial -40C to +100C | Industrial -40C to +100C | Industrial -40C to +100C | Industrial -40C to +100C | Extended -40C to +125C |
| Process / Core Voltage | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V | 20 nm / 0.9 V |
Key Differentiators
- Largest package and highest user I/O count in the Arria 10 GX 115K-LE family (vs 10AX115H2F34I2SG)
- Speed grade 1 yields lower dynamic power vs grade 2 same-die parts (vs 10AX115H2F34I2SG)
- Industrial temperature range for outdoor and factory deployments (vs 10AX115N1F40E1SG)
Design Notes
Estimated: The 1517-ball FC-FBGA at 1.0 mm pitch requires an 8-layer PCB with 0.5 oz copper on outer layers and a 0.4 mm via pad stack. Microvias (laser-drilled) are mandatory for the breakout region; staggered or stacked microvia constructions are supported by most PCB vendors. Recommend a 1.6 mm finished board thickness to maintain planarity during reflow.
Estimated: The Arria 10 10AX115 at full transceiver and DSP utilization typically draws 15-25 W from a 0.9 V core rail. Designers must sequence VCC, VCCP, VCCERAM, VCCPT, and VCCHPG using the Intel Arria 10 Power Management User Guide reference design. A dual-phase PWM controller such as the LTC3614 or ISL9444 typically supplies the core. Power-up ramp times must stay within the 0.2 ms to 100 ms window to avoid POR latch-up.
Estimated: At 20 W dissipation on the 1517-ball FC-FBGA (theta_JA ~5 C/W with a 25x25 mm thermal copper pad and airflow of 200 LFM), the junction rises ~100C above ambient. A heatsink of 1 C/W or larger is recommended above 15 W, or a 30x30 mm copper coin on the top side of the BGA. The Speed Grade 1 device typically dissipates 8-12% less than Grade 2 at the same frequency.
Common pitfalls: (1) Do not connect JTAG TCK to a generic GPIO - it must be a 1.8 V tolerant Schmitt-triggered input per the Arria 10 Pin Connection Guidelines. (2) Leave unused transceiver channels powered down through Quartus Prime assignment, never floating. (3) PCIe reference clock must meet the 100 ppm accuracy spec or link training fails. (4) Configuration MSEL pins must match the selected configuration scheme (AS, PS, JTAG, FPP) at board power-up - changing this on a populated board requires a rework.
Multi-gigabit transceivers running at 14.1 Gbps require 100 ohm differential routing with 6 mil trace width and 4 mil spacing on the top microstrip layer above a continuous ground plane. Skew between P and N must be under 1 ps per inch; length tuning is mandatory. AC-coupling capacitors (0.1 uF 0402 X7R) are required on every transmit pair. Eye margins of 200 mV and 80 ps are typical post-equalization for a 14.1 Gbps link.
Compliance Information
RoHS and lead-free per Intel product page; halogen-free status not explicitly published. AEC-Q100 not applicable - this is an FPGA, not an automotive-grade IC; for automotive, choose an automotive-qualified variant.
