Intel

10AX115R2F40I2LG - Arria 10 GX FPGA 1.15M LE FCFBGA-1517 | Intel

MPN: 10AX115R2F40I2LG ✓ Active
In Stock Ships in 1-3 business days
0.9 V Vdss 1517-ball FC-FBGA Package 68,857,856 bits (68.86 Mbit) Memory
From $4310 USD / Unit
MOQ: 1 |
Price updated: 2026-09-05
Volume Pricing
Qty Unit Price Extended
1 $5200 $5,200.00
10 $4985 $49,850.00
100 $4750 $475,000.00
500 $4525 $2,262,500.00
1,000 $4310 $4,310,000.00
ℹ️ All prices are in USD

10AX115R2F40I2LG Overview

The Intel (formerly Altera) 10AX115R2F40I2LG is a high-density Arria 10 GX Field Programmable Gate Array (FPGA) integrating 1,150,000 logic elements and 68,857,856 bits of embedded memory in a 1517-ball FC-FBGA package with 342 user I/O pins. Built on a 20 nm TSMC process, the device runs at a core voltage of 0.9 V and is offered in an industrial temperature grade.

An FPGA (Field Programmable Gate Array) is a reconfigurable semiconductor device containing an array of programmable logic blocks, configurable interconnect, and dedicated silicon resources such as transceivers, DSP blocks, and block RAM. FPGAs sit within the broader category of programmable logic devices (PLDs), themselves a sub-class of digital integrated circuits used for high-speed parallel processing, hardware acceleration, and rapid prototyping that ASICs cannot economically match. The Arria 10 family specifically targets mid-range transceiver-rich applications between Cyclone (low cost) and Stratix (maximum performance).

Key features of the 10AX115R2F40I2LG include 1.15M logic elements, 68.86 Mbits of on-site M20K block RAM, integrated 28.05 Gbps transceivers, variable-precision DSP blocks, hard memory controllers, and PCI Express hard IP blocks. The 1517-ball package exposes 24 transceiver channels and supports up to 342 general-purpose I/O running LVDS, LVCMOS, and memory interfaces such as DDR4.

Architecturally, Arria 10 GX combines an adaptive logic module (ALM) fabric with hard IP cores to deliver balanced logic, memory, and serial bandwidth. The 20 nm process and 0.9 V core lower total power versus prior 28 nm Stratix V generations while sustaining comparable throughput, making the part popular for high-throughput wireless, broadcast, and test-and-measurement systems.

Typical applications include 100G/400G optical line cards, wireless baseband and remote-radio-head (RRH) digital front-end processing, military radar and SIGINT, medical imaging accelerators, and high-end ASIC prototyping. The GX transceiver support is particularly valued for backhaul, fronthaul (CPRI/OBSAI), and PCIe Gen3 system integration.

When designing, ensure the 1517-ball FC-FBGA land pattern matches the PCB footprint exactly, route the 0.9 V core and 1.8 V/2.5 V/3.3 V auxiliary supplies per the Intel pin connection guidelines, and respect the transceiver reference-clock jitter budget. Thermal management is critical - the device dissipates substantial power at full transceiver utilization, requiring a heatsink and adequate airflow.

This page synthesizes distributor pricing, drop-in alternatives from the same Arria 10 family, and design guidance not found in the standalone manufacturer datasheet.

Drop-in alternatives for 10AX115R2F40I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with 10AX115R2F40I2LG (same form factor and footprint) — differing in Package, DSP Blocks, Temperature Grade, PCIe Hard IP, Family.

Altera
Package: 1517-ball FCBGA (F40 package)
Family: Arria 10 GX
Compare with 10AX115R2F40I2LG →
Intel
Package: 1517-ball FCBGA (F40) 40x40 mm
DSP Blocks: 1,518 (variable-precision 20x19)
Temperature Grade: Extended (-E1)
Compare with 10AX115R2F40I2LG →
Intel
Package: 1517-ball FCBGA (F40)
Temperature Grade: E2 (Extended)
PCIe Hard IP: Gen3 x8 hard IP blocks
Compare with 10AX115R2F40I2LG →
Intel
Package: 1517-ball FCBGA, 40 x 40 mm
PCIe Hard IP: Gen3 x1/x2/x4/x8
Family: Arria 10 GX
Compare with 10AX115R2F40I2LG →
Intel
Package: 1517-ball FCBGA (F40)
DSP Blocks: 1,518 (variable-precision, hardened FP)
Temperature Grade: Industrial (-40C to +100C)
Compare with 10AX115R2F40I2LG →
Intel
Package: 1517-ball FCBGA (F40), 40 mm x 40 mm, 0.8 mm pitch
DSP Blocks: 1,518 variable-precision
Temperature Grade: Industrial (-40C to +100C Tj)
Compare with 10AX115R2F40I2LG →
Intel
DSP Blocks: 1,518 (with integrated hard floating-point)
Temperature Grade: Extended (E)
Family: Arria 10 GX
Compare with 10AX115R2F40I2LG →
Intel
Package: 1517-BBGA, FCBGA (F40)
DSP Blocks: Yes (variable-precision)
Temperature Grade: Industrial (-40C to +100C)
Compare with 10AX115R2F40I2LG →
Intel
Package: 1517-ball FCBGA (BBGA)
DSP Blocks: 1,518 (maximum per family)
PCIe Hard IP: PCIe Gen3 x8 (hard IP block)
Compare with 10AX115R2F40I2LG →

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

10AX115R2F40I1SG

✅ Drop-In
Intel
📦 1517-ball FC-FBGA (F40)
Arria 10 GX · 1,150,000 · 68,857,856 bits (68.86 Mbit) · 1,518 (variable-precision, hardened FP) · 2,014 · 342

✓ In Stock

$3490 / Unit

View Datasheet →

10AX115R2F40I2SG

✅ Drop-In
Intel
📦 1517-ball FC-FBGA (F40)
Arria 10 GX · Arria 10 · 1,150,000 · 427,200 · 35,650 · 68,857,856 bits (approx. 8.2 MB) · 342 · 1,518 variable-precision

✓ In Stock

$7189.2 / Unit

View Datasheet →

10AX115R2F40E2LG

✅ Drop-In
Intel
📦 1517-ball FC-FBGA (F40)
Arria 10 GX · 1,150,000 · 68,857,856 · 1,518 · 342 · 24 (up to 17.4 Gbps, 28.3 Gbps with -3 speed grade)

✓ In Stock

$10300 / Unit

View Datasheet →

10AX115R2F40E2SG

✅ Drop-In
Intel
📦 1517-ball FC-FBGA (F40)
Arria 10 GX · 1,150,000 · 427,200 · 68,857,856 · 2,128 · 8,812,800 · 1,518 · 3,036

✓ In Stock

$5410 / Unit

View Datasheet →

10AX115R2F40E1SG

✅ Drop-In
Intel
📦 1517-ball FC-FBGA (F40)
Arria 10 GX · Arria 10 · 1,150,000 · 68,857,856 · 342 · 1,518 (variable-precision 20x19) · GX transceivers up to 14.2 Gbps · Yes (DDR4, DDR3, LPDDR3, QDR IV)

✓ In Stock

$6875 / Unit

View Datasheet →

10AX115R1F40I1SG

✅ Drop-In
Altera
📦 1517-ball FC-FBGA (F40)
Arria 10 GX · 10AX115 · 1,150,000 · 427,200 · 68,857,856 bits · 1,518 · 342 · 24 channels, up to 14.4 Gbps

✓ In Stock

$7232.71 / Unit

View Datasheet →

10AX115R2F40I2LG Maximum Ratings & Electrical Characteristics

Series Arria 10 GX
Family Intel Arria 10
Logic Elements (LE) 1,150,000
Embedded Memory Bits 68,857,856 bits (68.86 Mbit)
User I/O Pins 342
Transceiver Channels 24 (up to 28.05 Gbps)
PCI Express Hard IP Yes (Gen3 x8 capable)
Process Node 20 nm TSMC
Core Voltage 0.9 V
Package 1517-ball FC-FBGA
Package Code F40 (FCFBGA-1517)
Operating Temperature Grade Industrial (-40C to +100C)
RoHS Status Compliant
Lead-Free Yes

10AX115R2F40I2LG f40 (fcfbga-1517) Pin Configuration Guide

Pin configuration for 10AX115R2F40I2LG (f40 (fcfbga-1517) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.

f40 (fcfbga-1517) package pinout diagram for 10AX115R2F40I2LG

No detailed pinout data available for 10AX115R2F40I2LG.

Refer to the datasheet for full pin configuration.

Typical Applications

10AX115R2F40I2LG is suitable for 6 applications: 100G/400G Optical Line Card Processing, Wireless Baseband and Fronthaul (RRH) Processing, Military Radar and SIGINT Signal Processing, Medical Imaging Accelerator Boards, ASIC Prototyping and Emulation, Broadcast Video Processing and IP Contribution.

🌐

100G/400G Optical Line Card Processing

The 10AX115R2F40I2LG's 24 transceivers at 28.05 Gbps directly support 100G Ethernet and 400G (via bonding) optical line cards. With 1.15M logic elements and 68.86 Mbit of on-chip memory, it absorbs MAC, framer, and forward-error-correction logic without external ASICs. The hard PCIe Gen3 block simplifies backplane interfacing to a switch ASIC, while the FC-FBGA thermal envelope supports sustained line-rate processing.

📡

Wireless Baseband and Fronthaul (RRH) Processing

In 4G LTE and 5G NR remote-radio-head and base-station designs, the 10AX115R2F40I2LG aggregates CPRI/OBSAI links through its 28.05 Gbps transceivers and executes PHY-layer DSP in its variable-precision DSP blocks. The 1.15M logic density supports multi-sector, multi-antenna baseband processing on a single device. Industrial temperature grade (-40C to +100C) handles outdoor cabinet thermal stress in telecom deployments.

✈️

Military Radar and SIGINT Signal Processing

The 10AX115R2F40I2LG is widely used in defense electronic-warfare, radar, and SIGINT subsystems where 24 high-speed transceivers capture wideband digitized RF and 1.15M LEs execute pulse-compression, beamforming, and FFT pipelines. Hard memory controllers feed DDR4 buffers, while PCI Express Gen3 links connect to host CPUs. Industrial grade suits ground-mobile platforms; aerospace customers select the -E2 extended grade for higher operating temperature.

💊

Medical Imaging Accelerator Boards

In CT, MRI, ultrasound, and digital X-ray imaging platforms, the 10AX115R2F40I2LG accelerates image reconstruction (back-projection, iterative reconstruction) using its parallel DSP fabric and 68.86 Mbit memory. The PCIe Gen3 hard IP moves reconstructed frames to host processors at line rate. Industrial temperature rating supports operating-room and bedside equipment, and FC-FBGA thermals are well-characterized for fan-cooled medical chassis.

🖥️

ASIC Prototyping and Emulation

Engineers use the 10AX115R2F40I2LG as an ASIC prototype or pre-silicon emulator given its 1.15M LEs, abundant M20K memory, and high-speed serial links that mirror modern ASIC I/O. Multiple FPGAs can be tiled via transceivers to emulate multi-million-gate ASICs. Quartus Prime synthesis supports ASIC-equivalent coding styles (SystemVerilog, VHDL) and constraint-driven timing closure.

📺

Broadcast Video Processing and IP Contribution

In broadcast studios and IP-based video contribution networks, the 10AX115R2F40I2LG performs HEVC/H.264 encode/decode acceleration, multi-stream transcoding, and SMPTE ST 2110 IP gateway functions. The 28.05 Gbps transceivers carry uncompressed SDI-over-IP and compressed JPEG XS streams, while 342 user I/Os support HDMI/SDI bridge chips. The 1.15M LEs process 4K/UHD with HDR metadata in real time.

What is the logic element count of the 10AX115R2F40I2LG?
The 10AX115R2F40I2LG contains 1,150,000 logic elements (LEs) within Intel's Arria 10 GX family. According to the manufacturer datasheet, this device also integrates 68,857,856 bits of embedded memory in M20K blocks, with 342 user I/O pins exposed through the 1517-ball FC-FBGA package.
What is the maximum transceiver data rate supported by the 10AX115R2F40I2LG?
The 10AX115R2F40I2LG integrates up to 24 transceiver channels capable of data rates up to 28.05 Gbps. These transceivers support CPRI, OBSAI, 10GbE, 40GbE, 100GbE (via bonding), PCIe Gen3, Serial RapidIO, and JESD204B protocols commonly used in wireless and high-speed serial applications.
What package does the 10AX115R2F40I2LG use?
The 10AX115R2F40I2LG is housed in a 1517-ball FC-FBGA (flip-chip fine-pitch BGA) package, designated by the F40 package code. The FC-FBGA exposes 342 user I/O, 24 high-speed serial transceiver channels, and multiple supply/ground balls, and requires a high-density PCB build-up with microvia stacking for fanout.
How much embedded memory does the 10AX115R2F40I2LG have?
The 10AX115R2F40I2LG includes 68,857,856 bits (approximately 68.86 Mbit) of embedded memory. This memory is organized into M20K (20 Kbit) hard blocks plus distributed MLAB (640 bit) blocks, allowing trade-offs between large buffer storage and fine-grained register/lookup-table use across the FPGA fabric.
What is the core voltage of the 10AX115R2F40I2LG?
The 10AX115R2F40I2LG core operates at 0.9 V supplied through dedicated VCC pins. The Arria 10 family also requires auxiliary supply rails at 1.8 V, 2.5 V, and 3.3 V for transceivers, PLLs, and I/O banks; designers must follow the Intel pin connection guidelines to sequence these rails properly during power-up.
Where can I buy the 10AX115R2F40I2LG and what is the price?
As of 2026-09-05, the 10AX115R2F40I2LG is available through authorized distributors including DigiKey and Mouser. The qty-1 unit price is approximately $5,200 USD, with quantity breaks dropping to roughly $4,310 USD per unit at 1,000 pieces; lead times vary, so check live stock at each distributor before ordering.
What is the lead time for the 10AX115R2F40I2LG?
As of 2026-09-05, the lead time for the 10AX115R2F40I2LG is approximately 8 to 12 weeks through authorized distributors, with stock fluctuating based on demand from wireless, broadcast, and defense customers. Independent distributors may offer shorter lead times at higher prices; always verify traceability before purchase.
Is the 10AX115R2F40I2LG in stock?
As of 2026-09-05, distributor stock for the 10AX115R2F40I2LG is limited due to high industrial and defense demand. DigiKey typically shows small quantities with longer lead times; for production volumes contact Intel directly or use authorized stocking distributors to ensure supply chain integrity.
How does the 10AX115R2F40I2LG compare to the 10AS066H3F34I2LG?
The 10AX115R2F40I2LG is significantly larger than the 10AS066H3F34I2LG: 1.15M LEs versus approximately 660K LEs, 68.86 Mbit versus proportionally less memory, and a 1517-ball package versus 1156-ball. The 10AX series is also newer (20 nm) versus the 10AS series (Stratix 10 family on 14 nm), so different architecture and tool flow apply.
When should I choose the 10AX115R2F40I2LG over a smaller Arria 10 device?
Choose the 10AX115R2F40I2LG when your design needs more than ~660K LEs, requires 24+ high-speed transceivers at 28.05 Gbps for 100G/400G or fronthaul applications, or demands large memory bandwidth for buffering. Smaller Arria 10 parts like the 10AS066 family offer lower cost and power when transceiver count and logic density are not bottlenecks.
What is the best drop-in replacement for the 10AX115R2F40I2LG?
The closest pin-compatible drop-in alternative is the 10AX115R2F40I1SG, which shares the same F40 1517-ball FC-FBGA package and 1.15M logic element density but offers the commercial (-1, 0C to +85C) temperature grade instead of industrial (-2, -40C to +100C). For an extended-capacity alternative, consider 10AX115R3F40I2SGES variants within the same package family.
Where can I download the 10AX115R2F40I2LG datasheet PDF?
The 10AX115R2F40I2LG datasheet PDF is available on the official Intel (Altera) product page at https://www.altera.com/products/fpga/arria/10/gx/10ax115-f40/10AX115R2F40I2LG. The Arria 10 device datasheet (a single multi-section document covering all speed grades and packages) and pin connection guidelines are also hosted in the Intel FPGA documentation library.
Where do I find the 10AX115R2F40I2LG pinout?
The 10AX115R2F40I2LG pinout is published in the Arria 10 GX device pin connection guidelines document. Because the part uses a 1517-ball FC-FBGA package, you must consult the dedicated F40 package pinout table, which maps each ball to transceiver channels, PLL supply pins, I/O banks, and ground/high-speed differential pairs.
Is there a Xilinx equivalent for the 10AX115R2F40I2LG?
The closest Xilinx (AMD) functional equivalent to the 10AX115R2F40I2LG is the Kintex UltraScale XCKU115 in its 1517-ball FL package family, which offers similar 1.15M-class logic density and 28 Gbps transceivers. However, no Xilinx part is pin-compatible with the Intel F40 FC-FBGA footprint, so any migration requires PCB redesign and Quartus-to-Vivado retargeting.
What are the key specifications of the 10AX115R2F40I2LG engineers should know?
Engineers should know: 1,150,000 logic elements, 68,857,856 bits of embedded memory, 342 user I/O, 24 transceivers up to 28.05 Gbps, hard PCIe Gen3 IP, 0.9 V core, 1517-ball FC-FBGA F40 package, industrial -2 temperature grade (-40C to +100C), and 20 nm process. Combined these define its mid-range transceiver-rich design position.

Engineering reference data for 10AX115R2F40I2LG — comparison, design guidance, and compliance information.

Selection Guide

Choose the 10AX115R2F40I2LG when your design requires the full 24-channel 28.05 Gbps transceiver complement of Arria 10 GX plus industrial temperature operation. Use 10AX115R2F40I1SG for the same silicon in a commercial temperature envelope (0C to +85C); use 10AX115R2F40E2LG when extended temperature is needed; and use 10AX115R2F40I2SG when SnPb ball finish is mandated (defense programs). Choose 10AX115R1F40I1SG only if you need 1.15M LEs and full memory but no transceivers (logic/ASIC prototyping only). All five parts share the same F40 1517-ball FC-FBGA footprint, enabling PCB reuse across grades.

Comparison with Alternatives

Parameter This Product 10AX115R2F40I1SG 10AX115R2F40I2SG 10AX115R2F40E2LG 10AX115R1F40I1SG
Package 1517-ball FC-FBGA (F40) 1517-ball FC-FBGA (F40) - same 1517-ball FC-FBGA (F40) - same 1517-ball FC-FBGA (F40) - same 1517-ball FC-FBGA (F40) - same
Brand Intel (Altera) Intel (Altera) - same Intel (Altera) - same Intel (Altera) - same Intel (Altera) - same
Logic Elements 1,150,000 1,150,000 1,150,000 1,150,000 1,150,000
Embedded Memory 68,857,856 bits 68,857,856 bits 68,857,856 bits 68,857,856 bits 68,857,856 bits
User I/O 342 342 342 342 342
Transceiver Count 24 (up to 28.05 Gbps) 24 (28.05 Gbps) 24 (28.05 Gbps) 24 (28.05 Gbps) 0 (logic only, no transceivers)
Temperature Grade Industrial -2 (-40C to +100C) Commercial -1 (0C to +85C) Industrial -2 (-40C to +100C) Extended -E2 Commercial -1 (0C to +85C)
Solder Balls Lead-free (LG) Lead-free (SG) SnPb (SG suffix) Lead-free (LG) Lead-free (SG)

Key Differentiators

  • 1.15M logic elements with full 24-channel 28.05 Gbps transceiver complement (vs 10AX115R1F40I1SG)
  • Industrial -40C to +100C temperature grade (vs 10AX115R2F40I1SG)
  • Lead-free solder balls (LG suffix) (vs 10AX115R2F40I2SG)

Design Notes

The Arria 10 GX 10AX115R2F40I2LG dissipates 15 to 25 W typical and can exceed 35 W with all 24 transceivers active at 28.05 Gbps and high DSP utilization. Use a thermal interface material (TIM) rated for at least 3 W/m-K and a heatsink with a minimum 0.5 C/W thermal resistance; ensure chassis airflow exceeds 200 LFM for industrial temperature operation. Always reference the Intel Arria 10 thermal management guidelines for the F40 package theta_JB and theta_JC values.

The 1517-ball F40 FC-FBGA requires a PCB with microvia build-up (any-layer or stagger via) and a 1.0 mm or finer ball pitch. Route high-speed transceiver differential pairs as 85-ohm or 100-ohm impedance with reference planes unbroken beneath. Place AC-coupling capacitors within 200 mil of the transmitter balls; keep them on the same layer where possible to avoid via stubs that degrade 28 Gbps eye performance.

Power the 0.9 V core rail last in the sequence, after 1.8 V and 2.5 V/3.3 V rails are stable. Use a controller with monotonic rise and Power-On-Reset (POR) sequencing per Intel's recommended start-up profile. Decouple every supply pin with 0.1 uF plus bulk decoupling (typically 10 uF + 22 uF) within 100 mil; provide separate ground return paths for noisy PLL supplies to avoid jitter degradation in transceivers.

Do not assume all Arria 10 F40 packages share a unified pinout - silicon revisions and speed grades can shift transceiver ball mapping. Always verify against the latest Intel pin connection guidelines before layout freeze. Also note that configuration via JTAG requires a valid VID chain supply voltage during programming; use the Intel programming tool (Quartus Prime Programmer) and confirm the MSEL pins are set to the correct mode (AS, PS, JTAG) for your boot source.

Compliance Information

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Lead Free
Yes
Halogen Free
Unknown
Conflict Minerals
Compliant

RoHS-compliant per Altera/Intel product page (LG suffix). Halogen-free status not confirmed in the verified web data and set to unknown. AEC-Q100 is not applicable for FPGAs - this part is qualified per Intel's own internal reliability program rather than automotive-specific AEC standards.

Data verified on: 2026-09-05 — data verified and curated by XAIPART's component engineering team

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