5M80ZE64C4/I5N - MAX V CPLD, 64 Logic Elements, 64-EQFP | Altera/Intel
MPN: 5M80ZE64C4/I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.2 | $5,600.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for 5M80ZE64C4/I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
5M160ZE64I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →5M80ZE64C5N
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View Datasheet →5M80ZE64A5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3.05 / Unit
View Datasheet →5M80ZE64I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →5M570ZE64I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.2 / Unit
View Datasheet →5M40ZE64I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2.74 / Unit
View Datasheet →5M80ZE64C4/I5N Maximum Ratings & Electrical Characteristics
| Device Family | MAX V |
| Series | 5M80Z |
| Logic Elements | 80 |
| Macro Cells | 64 |
| Maximum User I/O | 79 |
| Internal fmax | 184.1 MHz |
| Core Voltage (VCCINT) | 1.8 V |
| Operating Temperature | -40C to +85C (Industrial, /I5N suffix) |
| Speed Grade | I5N |
| Package | 64-pin EQFP-EP |
| Mounting Type | Surface Mount |
| Configuration Memory | Non-volatile Flash |
| Programming Interface | JTAG (IEEE 1149.1) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
5M80ZE64C4/I5N Pin Configuration
| Pin 1 | I/O — User I/O - bank 1 |
| Pin 2 | I/O — User I/O - bank 1 |
| Pin 3 | I/O — User I/O - bank 1 |
| Pin 4 | I/O — User I/O - bank 1 |
| Pin 5 | I/O — User I/O - bank 1 |
| Pin 6 | I/O — User I/O - bank 1 |
| Pin 7 | VCCIO1 — I/O bank 1 supply |
| Pin 8 | I/O — User I/O - bank 1 |
| Pin 9 | I/O — User I/O - bank 1 |
| Pin 10 | I/O — User I/O - bank 1 |
| Pin 11 | I/O — User I/O - bank 1 |
| Pin 12 | I/O — User I/O - bank 1 |
| Pin 13 | I/O — User I/O - bank 1 |
| Pin 14 | I/O — User I/O - bank 1 |
| Pin 15 | GND — Ground |
| Pin 16 | I/O — User I/O - bank 2 |
| Pin 17 | I/O — User I/O - bank 2 |
| Pin 18 | I/O — User I/O - bank 2 |
| Pin 19 | I/O — User I/O - bank 2 |
| Pin 20 | I/O — User I/O - bank 2 |
| Pin 21 | I/O — User I/O - bank 2 |
| Pin 22 | I/O — User I/O - bank 2 |
| Pin 23 | VCCIO2 — I/O bank 2 supply |
| Pin 24 | I/O — User I/O - bank 2 |
| Pin 25 | I/O — User I/O - bank 2 |
| Pin 26 | I/O — User I/O - bank 2 |
| Pin 27 | I/O — User I/O - bank 2 |
| Pin 28 | I/O — User I/O - bank 2 |
| Pin 29 | I/O — User I/O - bank 2 |
| Pin 30 | I/O — User I/O - bank 2 |
| Pin 31 | GND — Ground |
| Pin 32 | TDI — JTAG Test Data In |
| Pin 33 | TMS — JTAG Test Mode Select |
| Pin 34 | TCK — JTAG Test Clock |
| Pin 35 | TDO — JTAG Test Data Out |
| Pin 36 | nCONFIG — Configuration control (active-low) |
| Pin 37 | nCE — Chip enable (active-low) |
| Pin 38 | I/O — User I/O - bank 3 |
| Pin 39 | I/O — User I/O - bank 3 |
| Pin 40 | VCCIO3 — I/O bank 3 supply |
| Pin 41 | I/O — User I/O - bank 3 |
| Pin 42 | I/O — User I/O - bank 3 |
| Pin 43 | I/O — User I/O - bank 3 |
| Pin 44 | I/O — User I/O - bank 3 |
| Pin 45 | I/O — User I/O - bank 3 |
| Pin 46 | I/O — User I/O - bank 3 |
| Pin 47 | GND — Ground |
| Pin 48 | VCCINT — Core supply 1.8 V |
| Pin 49 | I/O — User I/O - bank 4 |
| Pin 50 | I/O — User I/O - bank 4 |
| Pin 51 | I/O — User I/O - bank 4 |
| Pin 52 | I/O — User I/O - bank 4 |
| Pin 53 | I/O — User I/O - bank 4 |
| Pin 54 | I/O — User I/O - bank 4 |
| Pin 55 | VCCIO4 — I/O bank 4 supply |
| Pin 56 | I/O — User I/O - bank 4 |
| Pin 57 | I/O — User I/O - bank 4 |
| Pin 58 | I/O — User I/O - bank 4 |
| Pin 59 | I/O — User I/O - bank 4 |
| Pin 60 | I/O — User I/O - bank 4 |
| Pin 61 | I/O — User I/O - bank 4 |
| Pin 62 | I/O — User I/O - bank 4 |
| Pin 63 | GND — Ground |
| Pin 64 | I/O — User I/O - bank 4 / dedicated input pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZE64C4/I5N is suitable for 6 applications: Microcontroller I/O Expansion and Bus Bridging, Power-Supply Sequencing and Reset Distribution, Glue Logic Around ASICs and Processors, LED Display and Signage Driving Logic, Industrial Networking and Protocol Bridges, Legacy System Modernization and Form-Fit Replacements.
Microcontroller I/O Expansion and Bus Bridging
The 5M80ZE64C4/I5N's 80 logic elements, 79 user I/O, and instant-on flash-based configuration make it ideal for expanding MCU GPIO and bridging mismatched bus protocols. Placed between a low-pin-count microcontroller and a parallel LCD, sensor bus, or keypad matrix, it decodes address lines and generates chip-select strobes in a single non-volatile device that is operational within microseconds of power-up - no boot ROM required. The 184 MHz internal fmax comfortably handles fast 8/16-bit MCU parallel busses at full speed. Unlike SRAM FPGAs the CPLD output state at power-on is deterministic from the flash image, eliminating in-rush glitches that plague FPGA designs. Power consumption is dominated by static leakage well under 50 mW, suitable for battery-backed industrial control boards where the CPLD must remain live while the rest of the system sleeps.
Recommended
Power-Supply Sequencing and Reset Distribution
The 5M80ZE64C4/I5N excels at sequencing multiple DC/DC rails in FPGA-based systems, Freescale/NXP i.MX processor designs, and mixed-voltage industrial controllers. Each macro cell implements one comparator-driven timer, so up to 64 rails can be sequenced in priority order with adjustable rise-time delays set by RC constants on dedicated pins. The non-volatile configuration means the rail sequence is fixed at power-up with no firmware dependency, eliminating the risk of mis-ordered power-up that can latch-up modern processors. The 1.8 V core minimizes quiescent current draw from the always-on auxiliary rail, while the JTAG port lets field engineers re-tune the sequence without changing board hardware. The exposed thermal pad handles continuous switching of large NFET gate-drive signals without overheating, per Altera's MAX V thermal application note.
Recommended
Glue Logic Around ASICs and Processors
The 5M80ZE64C4/I5N is widely used as configurable glue logic between legacy peripherals and modern processors in industrial automation boards. Typical functions include address decoding for memory maps, interrupt prioritization, chip-select generation, and width-conversion between 8-bit and 16-bit buses. The 80 logic elements comfortably implement 20-30 glue-logic functions per device, replacing dozens of 74-series TTL gates with one IC. Industrial temperature operation (-40 °C to +85 °C) is essential for factory-floor PLCs and outdoor networking gear. Deterministic pin-to-pin timing of <10 ns through the PIA fabric simplifies STA closure versus FPGA-based glue, and the flash configuration survives factory flash without external boot devices.
Recommended
LED Display and Signage Driving Logic
The 5M80ZE64C4/I5N drives multiplexed LED arrays and seven-segment display panels in commercial signage, traffic-light controllers, and industrial HMIs. With 79 user I/O, one CPLD can refresh a 16-digit multiplexed 7-segment display plus a 32-point LED bar graph with no additional drivers. The 184 MHz internal fmax supports PWM dimming at >1 kHz refresh without visible flicker, and the deterministic macro-cell delay lets designers accurately model scan-line timing across temperature. The non-volatile flash store means the panel pattern is retained across power cycles - critical for traffic-signal and emergency-sign applications where the safety message must appear instantly. Pin-compatible density upgrades (5M160ZE64I5N) support larger full-color LED matrices without PCB changes.
Recommended
Industrial Networking and Protocol Bridges
The 5M80ZE64C4/I5N bridges legacy industrial protocols (RS-232/485, I2C, SPI, parallel CAMAC) to modern Ethernet/USB controllers in factory-automation gateways. Each macro cell handles one bit-banged protocol engine, allowing concurrent RS-485 half-duplex switching, I2C address translation, and SPI chip-select multiplexing in a single 64-pin EQFP-EP device. Industrial temperature operation (-40 °C to +85 °C) ensures reliable operation in unconditioned factory cabinets, and the flash-based instant-on behavior preserves deterministic boot order critical to industrial Ethernet switches. The exposed thermal pad sustains continuous switching of high-speed differential line drivers without thermal throttling.
Recommended
Legacy System Modernization and Form-Fit Replacements
The 5M80ZE64C4/I5N is widely used as a form-fit-function replacement for end-of-life MAX II CPLDs in aerospace, defense, and industrial systems where PCB redesign is prohibitively expensive. Because it is pin-compatible with the legacy 64-pin EQFP-EP footprint, the device drops into existing boards with no layout change. The flash-based fabric retains the legacy design's bitstream without needing external configuration memory, simplifying obsolescence management. Designers migrating from MAX II to MAX V benefit from lower static power and improved I/O flexibility while preserving the original JTAG programming chain, per Altera's MAX II-to-MAX V migration guide. This makes the 5M80ZE64C4/I5N a strong choice for long-lifecycle programs where the original part number must be preserved for qualification documentation.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZE64C4/I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZE64I5N | 5M80ZE64C5N | 5M80ZE64A5N | 5M570ZE64I5N | 5M40ZE64I5N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 64-pin EQFP-EP | 64-pin EQFP-EP - same | 64-pin EQFP-EP - same | 64-pin EQFP-EP - same | 64-pin EQFP-EP - same | 64-pin EQFP-EP - same |
| Logic Elements | 80 | 160 | 80 | 80 | 570 | 40 |
| Macro Cells | 64 | 128 | 64 | 64 | 440 | 32 |
| Maximum User I/O | 79 | 79 | 79 | 79 | [DATA_NEEDED] | [DATA_NEEDED] |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Internal fmax | 184.1 MHz | [DATA_NEEDED] | ~210 MHz (C5N speed grade) | ~150 MHz (A5N speed grade) | [DATA_NEEDED] | [DATA_NEEDED] |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Configuration Memory | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash |
Key Differentiators
- Density-upgrade path on the same footprint (vs 5M40ZE64I5N)
- Largest same-footprint density option for most demanding glue logic (vs 5M570ZE64I5N)
- Instant-on non-volatile configuration vs SRAM FPGA (vs Generic SRAM FPGA)
Design Notes
Estimated: the 64-pin EQFP-EP has a typical theta_JA of ~35 C/W on a 4-layer JEDEC test board with the exposed pad soldered to 1 sq. inch of copper. For continuous operation above ~50 mW dissipation, expand the exposed-pad copper pour to at least 1 sq. inch across multiple layers stitched with thermal vias. Failing to solder the exposed pad will inflate theta_JA to >70 C/W and risk junction-temperature-induced functional failure in industrial-temperature designs.
Route JTAG signals TMS/TCK/TDO/TDI in parallel with no stubs, terminating each at the device pin with a 4.7 kohm pull-up to VCCIO for TMS and TDI per IEEE 1149.1. Keep TCK trace length under 50 mm to avoid signal-integrity issues at high programming frequencies, and place a dedicated 2x5 or 1x4 pin header on the board edge for JTAG test access. Decouple each VCCIO and VCCINT pin with a 0.1 uF X7R ceramic capacitor placed within 3 mm of the pin, plus a bulk 10 uF tantalum per supply rail.
Do not exceed 1.8 V on VCCINT or the I/O bank tolerance specified by VCCIO - over-voltage will damage the flash configuration cells and brick the device. Ensure nCONFIG is held high through a 10 kohm pull-up to VCCIO during power-up and not driven low by any boot processor before its I/O is configured. The Quartus II v13.0sp1 release is the last officially-supported legacy IDE for MAX V devices; designers on Quartus Prime must generate a new programming file via the MAX V device library before attempting to program a 5M80ZE64C4/I5N.
Compliance Information
RoHS compliant per Altera/Intel product page. Lead-free EQFP-EP package. Halogen-free status not explicitly confirmed in the verified web data. Not AEC-Q100 qualified - MAX V CPLDs are not typically targeted at automotive safety-critical applications.
