EP1M350F780C5ES - Mercury FPGA 350K Gates 780-FBGA | Altera
MPN: EP1M350F780C5ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $198 | $19,800.00 |
| 500 | $165 | $82,500.00 |
| 1,000 | $142 | $142,000.00 |
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View Datasheet →EP1M350F780C5ES Maximum Ratings & Electrical Characteristics
| Family | Mercury (EP1M) |
| Logic Elements / Cells | 14,400 |
| Equivalent System Gates | 350,000 |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V nominal) |
| Transceivers | Integrated high-speed SERDES with CDR |
| Transceiver Data Rate | Up to 1.25 Gbps per channel |
| I/O Voltage Banks | Multiple, supporting mixed-voltage interfaces |
| Package | 780-pin FC-FBGA (Flip-Chip BGA) |
| Package Dimensions | 29 mm x 29 mm |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | 0C to +85C (commercial) |
| Architecture | LUT-based with embedded CDR transceivers |
| Compliance | RoHS (per distributor listing; status: unknown) |
| Lead-Free | yes |
EP1M350F780C5ES 29 mm x 29 mm Pin Configuration Guide
Complete pinout information for EP1M350F780C5ES (29 mm x 29 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1M350F780C5ES.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1M350F780C5ES is suitable for 6 applications: Multi-Gigabit Serial Backplane, Gigabit Ethernet Line Card, SONET/SDH Mapper Framer, Fibre Channel Switch Port, Serial RapidIO Bridge, Custom SERDES Interface ASIC Replacement.
Multi-Gigabit Serial Backplane
The EP1M350F780C5ES is well-suited to multi-gigabit serial backplane designs in communications equipment because its integrated 1.25 Gbps CDR-capable transceivers eliminate the need for an external PHY on each serial channel. With 350K system gates and 14,400 cells, the device can perform framing, encoding, and link-layer glue logic in addition to the SERDES function, replacing what would otherwise be a two-chip solution. Designers typically pair the device with a 100-ohm differential backplane and use the embedded CDR to recover clocks from incoming data streams without external components. This consolidation reduces board area, BOM cost, and signal-integrity risk versus using a separate transceiver plus FPGA approach.
Recommended
Gigabit Ethernet Line Card
In Gigabit Ethernet line cards the EP1M350F780C5ES serves as both the SERDES PHY and the framing/aggregation logic. Each integrated transceiver channel supports the 1.25 Gbps serial rate required for 1000BASE-X, and the LUT-based fabric implements MAC, framing, and traffic management functions on the same die. Using a single Mercury device per line card simplifies the BOM and shortens the design cycle versus a separate PHY-plus-FPGA architecture. Designers should follow Altera's reference designs for GMII/RGMII connections to the host MAC and use the embedded CDR to recover clocks cleanly from the SFP or PHY module.
Recommended
SONET/SDH Mapper Framer
SONET/SDH mapper framer designs use the EP1M350F780C5ES to implement OC-12 (622 Mbps) and OC-24 (1.244 Gbps) interfaces thanks to the integrated transceivers reaching 1.25 Gbps. The 14,400 logic cells provide ample capacity for section/line/path overhead processing, payload mapping, and pointer adjustments without external glue logic. According to Altera application notes, the Mercury architecture is well suited to telecom framer designs because of its deterministic timing and dedicated CDR circuitry. The 780-FBGA package supports the high I/O count required for backplane buses plus multiple serial links.
Recommended
Fibre Channel Switch Port
Fibre Channel switch port designs at 1 Gbps leverage the EP1M350F780C5ES to integrate the SERDES and the port-state machine on a single chip. With 1.25 Gbps CDR-capable transceivers the device easily meets the 1.0625 Gbps FC-1 line rate, and the 350K gates provide sufficient capacity for credit-based flow control, FC-2 framing, and link-state-machine logic. Designers typically implement 4-8 ports per Mercury device and use external SFP optical modules. The BGA-780 package enables the dense pin-out needed for multiple serial channels plus host bus connections.
Recommended
Serial RapidIO Bridge
Serial RapidIO bridges connecting DSP arrays, processors, and FPGAs across a backplane benefit from the EP1M350F780C5ES integrated transceivers running at 1.25 Gbps per lane. The Mercury fabric implements the RapidIO physical-layer encoder/decoder, link-layer state machine, and any application-layer packet processing, while the CDR circuits handle clock recovery from incoming serial streams. A single Mercury device can support multiple x1 or x4 lanes, replacing a PHY-plus-FPGA pair and reducing both board area and BOM cost. Designers should follow Altera's reference designs for 8B/10B encoding and link training.
Recommended
Custom SERDES Interface ASIC Replacement
Designers building custom SERDES-based interfaces (proprietary chip-to-chip links, medical imaging backplanes, or industrial high-speed buses) often turn to the EP1M350F780C5ES as a cost-effective alternative to a custom ASIC. The integrated CDR-capable transceivers handle the PHY function up to 1.25 Gbps, and the 14,400 logic cells allow arbitrary protocol encoding, framing, and link-layer customization - something a fixed-function ASIC cannot match. The 780-FBGA package provides hundreds of user I/Os for parallel interfaces to processors, sensors, or memory. This makes the Mercury family ideal for low-to-mid-volume products where ASIC NRE is not justified.
Recommended
Recommended Products Summary
Engineering reference data for EP1M350F780C5ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M350F780C5 | EP1M350B780C5 | EP1M350B780C6 | EP1M350B780I6 | EP1M350F672C7 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 780-FBGA (29x29) | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same | 672-FBGA - different |
| Logic Elements / Cells | 14,400 | 14,400 | 14,400 | 14,400 | 14,400 | 14,400 |
| System Gates | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 |
| Transceiver Data Rate | Up to 1.25 Gbps (CDR) | 1.25 Gbps | 1.25 Gbps | 1.25 Gbps | 1.25 Gbps | 1.25 Gbps |
| Core Voltage | 1.71V to 1.89V (1.8V nominal) | 1.71V to 1.89V | 1.71V to 1.89V | 1.71V to 1.89V | 1.71V to 1.89V | 1.71V to 1.89V |
| Speed Grade | C5 | C5 | C5 | C6 | I6 (industrial) | C7 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C | 0C to +85C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Integrated 1.25 Gbps CDR transceivers (vs EP1K100FC484-2 (general-purpose ACEX FPGA))
- Higher logic density than competitive FPGAs of its era (vs EP1K50FC484-2 (50K-gate ACEX))
- Commercial-grade C5 speed grade availability (vs EP1M350B780I6 (industrial grade))
Design Notes
Use a 100-ohm differential impedance for all SERDES lanes and route the P/N pair with matched length to within the tolerance specified in the Altera Mercury datasheet (typically within 5-10 mils). Maintain continuous reference planes on adjacent layers and avoid routing SERDES signals over plane splits. Decouple every VCCINT and VCCIO pin with a 0.1uF ceramic capacitor placed within 100 mils of the BGA ball, and add bulk 10-100uF tantalum or polymer capacitors near the device. BGA fanout should follow Altera's recommended via pattern to maintain manufacturability and yield.
The 780-FBGA package requires 6-8 layer PCB stackup with at least one dedicated ground plane and one dedicated power plane. SERDES high-speed signals should be routed on internal stripline layers with reference planes intact. Place the reference clock source as close as possible to the dedicated clock input pins, and use a low-jitter oscillator meeting the jitter specification in the Mercury datasheet. JTAG and configuration pins (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE) must be brought out to a header for programming; include a 10k pull-up on nCONFIG and a 10k pull-down on nSTATUS per Altera reference designs.
Estimated: Do not assume the EP1M350F780C5ES suffix indicates a faster speed grade - it denotes an ES screening step. Verify by reading the device markings or the lot paperwork. The Mercury family is end-of-life from Altera/Intel PSG, so any new production must source through independent distributors or aftermarket brokers. Confirm RoHS compliance and date code with your supplier before committing to production. Quartus II software versions older than 4.0 may not support this device, and modern Quartus Prime releases have dropped Mercury support entirely - retain a legacy toolchain for firmware updates.
Compliance Information
RoHS and REACH status not explicitly confirmed in verified web data; Mercury family devices from Altera were generally produced in lead-free (Pb-free) packages per distributor listings but full compliance documentation requires lot-specific certification. AEC-Q100 is not applicable as this is a commercial-grade PLD, not an automotive-qualified device.
