EP1M350F780C5N - 350K Gates Mercury FPGA w/ 1.25 Gbps CDR | Intel/Altera
MPN: EP1M350F780C5N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $142 | $14,200.00 |
| 250 | $128 | $32,000.00 |
| 500 | $115 | $57,500.00 |
Drop-in alternatives for EP1M350F780C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP1M350F780C5N Maximum Ratings & Electrical Characteristics
| Device Family | Mercury (EP1M350) |
| Equivalent Gates | 350,000 |
| Logic Cells (LEs) | 14,400 |
| User I/Os | 486 |
| Total Pins / Terminals | 780 |
| Logic Family | CMOS |
| Core Supply Voltage | 1.8 V |
| Package Type | FineLine BGA (FC-FBGA / PBGA-B780) |
| Terminal Form | Ball |
| Terminal Pitch | 1.000 mm |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to 85 C |
| Transceivers | Integrated high-speed CDR to 1.25 Gbps |
| Architecture | LUT-based, optimized for high performance |
EP1M350F780C5N fineline bga (fc-fbga / pbga-b780) Pin Configuration Guide
Complete pinout information for EP1M350F780C5N (fineline bga (fc-fbga / pbga-b780) package) with 780 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1M350F780C5N.
Refer to the datasheet for full pin configuration.
Estimated pin count: 780 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1M350F780C5N is suitable for 6 applications: Gigabit Ethernet Line Card / Switch Fabric, SONET/SDH OC-12 / OC-48 Telecom Backplane Aggregation, Industrial Imaging and Video Processing, Serial Backplane Aggregation in Custom Communications Equipment, ASIC Prototyping and Logic Emulation, Legacy Defence / Aerospace Serial-Link Systems.
Gigabit Ethernet Line Card / Switch Fabric
The EP1M350F780C5N's integrated 1.25 Gbps clock-data-recovery transceivers, combined with 14,400 logic cells and 486 user I/Os, make it well-suited to Gigabit Ethernet line cards, switch fabrics, and router forwarding engines. The on-chip CDR eliminates the need for external PHY chips, reducing BOM cost and board area. The 1.8V core supply keeps per-port power low, which is critical when aggregating many Gigabit links on one line card. Designers typically use the Mercury MAC IP core along with PCS logic implemented in LUTs to deliver multi-port Gigabit Ethernet switches. The fine-pitch 780-ball BGA also supports dense high-speed differential pair routing required for SGMII or 1000BASE-T PHYs.
Recommended
SONET/SDH OC-12 / OC-48 Telecom Backplane Aggregation
The 1.25 Gbps CDR transceivers integrated into the EP1M350F780C5N enable direct aggregation of SONET/SDH OC-12 (622 Mbps) and OC-48 (2.488 Gbps) backplane links. The 350K-gate Mercury die provides the logic capacity for STS-1/AU-3 mapping, pointer processing, and overhead termination in next-generation SONET/SDH equipment. The 486 user I/Os carry parallel overhead buses and backplane framing interfaces. Industrial temperature grading supports central-office deployment. Altera's Mercury datasheet documents the CDR's jitter tolerance (typically 0.15 UI) and the per-port FIFO depth needed for pointer adjustment, simplifying framer implementation in LUTs and embedded memory.
Recommended
Industrial Imaging and Video Processing
The EP1M350F780C5N's 14,400 logic cells and high user-I/O count (486) suit real-time image processing pipelines such as Camera Link frame grabbers, machine-vision inspection systems, and broadcast video format converters. LVDS/LVCMOS I/O banks receive Camera Link data at up to 680 Mbps, while on-chip block RAM buffers line-scan or area-scan data. The integrated 1.25 Gbps CDR transceivers can output processed streams over a single high-speed serial link to a host PC or backplane. Industrial 0-85 C operation accommodates factory-floor deployments. Quartus II IP libraries provide Camera Link receivers, Bayer demosaicing, and color-space conversion cores that map efficiently onto the Mercury LUT architecture.
Recommended
Serial Backplane Aggregation in Custom Communications Equipment
Custom communications equipment such as DSLAMs, CMTS upstream cards, and proprietary radio-head baseband units use the EP1M350F780C5N to aggregate multiple low-rate serial links into a single 1.25 Gbps uplink. The on-chip CDR provides the clock-recovery necessary for robust backplane operation across long FR-4 traces and connectors. The 780-ball FineLine BGA exposes enough differential pairs to handle 16+ full-duplex serial lanes alongside parallel datapath buses. Altera's SERDES and 8B/10B encoder IP cores are supported in Quartus II and map directly onto Mercury hard IP, minimizing logic cell overhead for the aggregation function.
Recommended
ASIC Prototyping and Logic Emulation
Designers used the EP1M350F780C5N as a high-capacity ASIC prototyping and logic emulation vehicle during the early 2000s because its 350K-gate density and 1.25 Gbps transceivers approximated production ASIC interfaces. Modern emulation workflows use larger devices, but legacy prototypes, IP validation boards, and university research platforms still rely on Mercury. The fine-pitch BGA exposes rich user I/O for logic analyzers, breakout boards, and daughter-card connections. Quartus II synthesis supports standard HDL flows (VHDL/Verilog), and the part integrates with on-chip debug tools such as SignalTap. Drop-in equivalents like EP1M350F780C5ES are still sought for emulation-board repair.
Recommended
Legacy Defence / Aerospace Serial-Link Systems
Long-lifecycle defence and aerospace programs continued to use Mercury FPGAs including the EP1M350F780C5N for serial-link upgrades to existing platforms. The 1.25 Gbps transceivers support Fibre Channel and custom serial links used in avionics, naval combat systems, and signal-intelligence platforms. The wide operating temperature range, hermetic-friendly BGA, and documented long-term reliability make Mercury attractive for retrofit programs that must outlive the original Altera production run. Modern equivalents such as Microchip RTG4 or Xilinx Virtex-4QV are radiation-hardened successors that require PCB redesign but offer similar serial bandwidth.
Recommended
Recommended Products Summary
Engineering reference data for EP1M350F780C5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M350F780C5ES | EP1M350F78016 | EP1M350F780C5 | EP1M350F780-C7 | EP1M350B780C7 | EP1M350B780C6 |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 780-ball FineLine BGA | 780-ball FineLine BGA - same | 780-ball FineLine BGA - same | 780-ball FineLine BGA - same | 780-ball FineLine BGA - same | 780-ball FineLine BGA - same | 780-ball FineLine BGA - same |
| Equivalent Gates | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 | 350,000 |
| Logic Cells | 14,400 | 14,400 | 14,400 | 14,400 | 14,400 | 14,400 | 14,400 |
| Speed Grade | C5 (1.25 Gbps CDR) | C5 ES | -16 | C5 | -C7 | C7 industrial | C6 industrial |
| RoHS Compliance | Yes (N suffix) | [DATA_NEEDED] | [DATA_NEEDED] | No (non-N) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Operating Temperature | 0 C to 85 C (commercial) | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C | Industrial (-40 to 100 C) | Industrial (-40 to 100 C) |
| Lifecycle Status | Obsolete | Obsolete (engineering sample) | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest-volume drop-in alternative is the engineering-sample EP1M350F780C5ES (vs EP1M350F780C5ES)
- Industrial-temperature -B variants extend the operating range (vs EP1M350B780C7, EP1M350B780C6)
- Older speed grades available in the same package for cost-down (vs EP1M350F780C5, EP1M350F780-C7)
Design Notes
Estimated: The 780-ball FineLine BGA at 1.0 mm pitch requires at minimum a 6-layer PCB stack-up with two dedicated ground planes and one dedicated 1.8V power plane. Micro-vias (8 mil laser-drilled) are required for fan-out from inner BGA balls; via-in-pad with copper-filled, plated-over vias is recommended to achieve <0.5 nH inductance per supply connection. Per the Mercury datasheet recommendation, place 0.1 uF X7R and 10 uF X5R decoupling capacitors within 100 mils of every VCCIO bank ball cluster.
The integrated 1.25 Gbps CDR transceivers require 100-ohm differential impedance-controlled routing for TX/RX pairs. Differential pair length matching must be within 5 mils of intra-pair and 50 mils of inter-pair for adequate jitter budget per Altera's Mercury Application Note AN-369. Use length-matched serpentine routing on outer microstrip layers over a continuous ground plane; avoid routing across plane splits or under noisy digital signals. Reference the Mercury datasheet's CDR Electrical Characteristics table for the eye-mask and jitter tolerance numbers used in link-budget validation.
Estimated: Common pitfalls when migrating to or programming the EP1M350F780C5N include (1) using an unsupported Quartus II version - Altera/Intel support for the Mercury family ended at Quartus II v13.0sp1; later releases drop device support, (2) failing to specify the correct speed grade and temperature grade in the Quartus device-selection dialog, which can result in un-routed designs or timing failures, and (3) using an older JTAG programmer that cannot supply the 1.8V VCCINT during configuration. Always generate BSDL and SOF files from a known-good Quartus II v13.0sp1 or earlier project, and validate on hardware before production.
Estimated: With 486 user I/Os switching simultaneously (worst-case synchronous bus design), the EP1M350F780C5N's simultaneous-switching-output (SSO) noise can corrupt PLL reference clocks and CDR inputs if decoupling is inadequate. Implement a 4-layer decoupling strategy: (1) 0.01 uF X7R within 30 mils of every VCCIO pin, (2) 0.1 uF X7R per I/O bank, (3) 10 uF X5R per supply rail, (4) bulk 100 uF tantalum or polymer on the 1.8V rail. The Mercury datasheet's SSO analysis example recommends synchronously controlling SSN with slew-rate adjustment on output drivers if your design crosses 200 MHz LVCMOS toggling.
Compliance Information
RoHS compliance inferred from the 'N' suffix in the part number per Altera naming convention; the Mercury family datasheet's compliance section was not in the verified data. Reach, halogen-free, and conflict-minerals status are not in the verified data and are marked unknown.
