EPF8636ALC84-4N - FLEX 8000 FPGA 6K Gates 84-PLCC | Altera
MPN: EPF8636ALC84-4N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.95 | $995.00 |
| 500 | $8.75 | $4,375.00 |
| 1,000 | $7.5 | $7,500.00 |
Drop-in alternatives for EPF8636ALC84-4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPF8636ALC84-4
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View Datasheet βEPF8636ALC84-4N Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Usable Gates | ~6,000 |
| Logic Elements (LEs) | 504 |
| Logic Array Blocks (LABs) | 63 |
| User I/Os | 68 |
| Package | 84-pin PLCC (J-Lead, plastic) |
| Process Technology | 0.42 Β΅m CMOS SRAM |
| Supply Voltage (VCC) | 5.0 V |
| I/O Standard | 5.0 V TTL/CMOS |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) |
| Configuration Method | Serial configuration device (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM |
| In-Circuit Reconfigurability (ICR) | Yes |
| Boundary Scan | IEEE 1149.1 JTAG |
EPF8636ALC84-4N Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (bank 1) |
| Pin 2 | I/O β General-purpose user I/O (bank 1) |
| Pin 3 | VCC β 5.0 V supply (I/O bank 1) |
| Pin 4 | I/O β General-purpose user I/O (bank 1) |
| Pin 5 | I/O β General-purpose user I/O (bank 1) |
| Pin 6 | I/O β General-purpose user I/O (bank 1) |
| Pin 7 | GND β Ground |
| Pin 8 | I/O β General-purpose user I/O (bank 1) |
| Pin 9 | I/O β General-purpose user I/O (bank 1) |
| Pin 10 | I/O β General-purpose user I/O (bank 1) |
| Pin 11 | I/O β General-purpose user I/O (bank 1) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β General-purpose user I/O (bank 1) |
| Pin 14 | I/O β General-purpose user I/O (bank 1) |
| Pin 15 | I/O β General-purpose user I/O (bank 1) |
| Pin 16 | I/O β General-purpose user I/O (bank 1) |
| Pin 17 | VCC β 5.0 V supply (I/O bank 1) |
| Pin 18 | I/O β General-purpose user I/O (bank 1) |
| Pin 19 | I/O β General-purpose user I/O (bank 1) |
| Pin 20 | I/O β General-purpose user I/O (bank 1) |
| Pin 21 | I/O β General-purpose user I/O (bank 1) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β General-purpose user I/O (bank 2) |
| Pin 24 | I/O β General-purpose user I/O (bank 2) |
| Pin 25 | I/O β General-purpose user I/O (bank 2) |
| Pin 26 | I/O β General-purpose user I/O (bank 2) |
| Pin 27 | VCC β 5.0 V supply (I/O bank 2) |
| Pin 28 | I/O β General-purpose user I/O (bank 2) |
| Pin 29 | I/O β General-purpose user I/O (bank 2) |
| Pin 30 | I/O β General-purpose user I/O (bank 2) |
| Pin 31 | I/O β General-purpose user I/O (bank 2) |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β General-purpose user I/O (bank 2) |
| Pin 34 | I/O β General-purpose user I/O (bank 2) |
| Pin 35 | I/O β General-purpose user I/O (bank 2) |
| Pin 36 | I/O β General-purpose user I/O (bank 2) |
| Pin 37 | VCC β 5.0 V supply (I/O bank 2) |
| Pin 38 | I/O β General-purpose user I/O (bank 2) |
| Pin 39 | I/O β General-purpose user I/O (bank 2) |
| Pin 40 | I/O β General-purpose user I/O (bank 2) |
| Pin 41 | I/O β General-purpose user I/O (bank 2) |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β General-purpose user I/O (bank 3) |
| Pin 44 | I/O β General-purpose user I/O (bank 3) |
| Pin 45 | I/O β General-purpose user I/O (bank 3) |
| Pin 46 | I/O β General-purpose user I/O (bank 3) |
| Pin 47 | VCC β 5.0 V supply (I/O bank 3) |
| Pin 48 | I/O β General-purpose user I/O (bank 3) |
| Pin 49 | I/O β General-purpose user I/O (bank 3) |
| Pin 50 | I/O β General-purpose user I/O (bank 3) |
| Pin 51 | I/O β General-purpose user I/O (bank 3) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β General-purpose user I/O (bank 3) |
| Pin 54 | I/O β General-purpose user I/O (bank 3) |
| Pin 55 | I/O β General-purpose user I/O (bank 3) |
| Pin 56 | I/O β General-purpose user I/O (bank 3) |
| Pin 57 | VCC β 5.0 V supply (I/O bank 3) |
| Pin 58 | I/O β General-purpose user I/O (bank 3) |
| Pin 59 | I/O β General-purpose user I/O (bank 3) |
| Pin 60 | I/O β General-purpose user I/O (bank 3) |
| Pin 61 | I/O β General-purpose user I/O (bank 3) |
| Pin 62 | GND β Ground |
| Pin 63 | nCONFIG β Configuration control (active-low) |
| Pin 64 | nSTATUS β Configuration status (active-low) |
| Pin 65 | CONF_DONE β Configuration done (active-high) |
| Pin 66 | DCLK β Configuration clock |
| Pin 67 | DATA0 β Configuration data input |
| Pin 68 | MSEL0 β Configuration mode select |
| Pin 69 | MSEL1 β Configuration mode select |
| Pin 70 | TCK β JTAG test clock (IEEE 1149.1) |
| Pin 71 | TMS β JTAG test mode select |
| Pin 72 | TDI β JTAG test data in |
| Pin 73 | TDO β JTAG test data out |
| Pin 74 | VCC β 5.0 V supply (core) |
| Pin 75 | GND β Ground (core) |
| Pin 76 | DEV_CLRn β Device clear (optional) |
| Pin 77 | DEV_OE β Device output enable (optional) |
| Pin 78 | I/O β General-purpose user I/O (bank 4) |
| Pin 79 | I/O β General-purpose user I/O (bank 4) |
| Pin 80 | I/O β General-purpose user I/O (bank 4) |
| Pin 81 | I/O β General-purpose user I/O (bank 4) |
| Pin 82 | I/O β General-purpose user I/O (bank 4) |
| Pin 83 | I/O β General-purpose user I/O (bank 4) |
| Pin 84 | I/O β General-purpose user I/O (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8636ALC84-4N is suitable for 6 applications: Industrial Glue Logic and Bus Bridging, Legacy Telecom Line-Card Interface Logic, Prototyping Platform and Educational FPGA Board, Aerospace and Defense Subsystem Controllers, Test and Measurement Backplane Instrumentation, Automotive and Heavy-Equipment ECU Peripherals.
Industrial Glue Logic and Bus Bridging
The EPF8636ALC84-4N's 6,000 usable gates and 68 user I/Os make it a natural fit for industrial glue-logic replacement, where it consolidates scattered 74-series TTL, PAL/GAL, and small PLDs into a single in-system-reconfigurable device. With 504 logic elements and 63 LABs, the part can replace 30-60 discrete logic packages while adding JTAG boundary-scan for production test. Designers use it to bridge legacy 8/16-bit Β΅C buses (8051, 68k) to modern peripherals, or to implement custom timing/sequencing that no off-the-shelf ASIC provides. The 5 V I/O and 0 Β°C-70 Β°C commercial range align with most factory-floor PLC and motor-drive subsystems.
Recommended
Legacy Telecom Line-Card Interface Logic
Telecom line-card and central-office designs of the late 1990s and early 2000s adopted the FLEX 8000 family for its deterministic timing and high I/O count. The EPF8636ALC84-4N is well suited to TDM bus formatting, HDLC framer glue, and serial-to-parallel conversion between E1/T1 framers and backplane ASICs. Its 68 user I/Os comfortably drive 8-bit data buses plus framing/clock/signalling overhead without external bus drivers. The in-system reconfigurability allows field-tariff or protocol upgrades without board removal, a major operational advantage for carriers. Modern replacements (Cyclone IV, MAX V) are not pin-compatible, so PLCC-84 retention keeps existing shelves in service.
Recommended
Prototyping Platform and Educational FPGA Board
Because the 84-pin PLCC J-Lead package is socket-friendly, the EPF8636ALC84-4N is a popular choice for university FPGA laboratories and rapid-prototyping boards where students swap devices for different lab exercises. The 6,000-gate density is enough to demonstrate finite-state machines, multipliers, simple CPUs (e.g., a 16-bit RISC-V subset), UARTs, SPI/I2C controllers, and basic VGA timing. In-system reconfigurability via EPC1/EPC1064 allows the same board to be reused across many lab sessions without reprogramming hardware. Its 5 V tolerance also makes the part tolerant of older lab power supplies.
Recommended
Aerospace and Defense Subsystem Controllers
The FLEX 8000 family has a long heritage in aerospace and defense subsystems where deterministic timing and radiation tolerance screening (when ordered through MIL-PRF-38535 flows) are valued. The EPF8636ALC84-4N in the commercial grade is used in non-flight ground-support equipment, while MIL-screened variants of the same die support flight-control interfaces, mission-computer I/O expansion, and radar signal-conditioning boards. The 68 user I/Os comfortably aggregate sensor buses, MIL-STD-1553 transceivers, and discrete discretes. Designers preserve the PLCC-84 footprint across ruggedized, conduction-cooled chassis.
Recommended
Test and Measurement Backplane Instrumentation
Test-and-measurement equipment such as logic analyzers, protocol exercisers, and ATE fixture controllers historically used FLEX 8000 FPGAs for pattern generation, timing-and-control sequencing, and bus protocol re-mapping. The EPF8636ALC84-4N's 504 logic elements implement 32-64 channel pattern generators with sub-10 ns edge accuracy, while 68 user I/Os drive both the DUT (device-under-test) interface and the instrument's local microcontroller. In-system reconfigurability enables field upgrades as new protocols are supported without returning the instrument. The PLCC-84 socket simplifies calibration swaps.
Recommended
Automotive and Heavy-Equipment ECU Peripherals
While the EPF8636ALC84-4N is commercial-grade (0 Β°C to 70 Β°C), its sibling FLEX 8000 devices with industrial screening are used in heavy-equipment ECUs for body controllers, dashboard multiplexing, and sensor aggregation. The 6,000-gate density and 68 I/Os aggregate CAN/LIN fan-out, switch-matrix scanning, and PWM channels. In-system reconfigurability allows OEM software updates over the diagnostic port without ECU replacement. Note: AEC-Q100 qualified parts do not exist in the FLEX 8000 family; for new automotive designs, Cyclone IV or MAX V are the recommended paths.
Recommended
Recommended Products Summary
Engineering reference data for EPF8636ALC84-4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8636ALC84-4 | EPF8636ALC84-3 | EPF8452ALC84-4N | EPF8452ALC84-4 | EPF8282ALC84-4N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same |
| Usable Gates | ~6,000 | ~6,000 | ~6,000 | ~4,000 | ~4,000 | ~2,500 |
| Logic Elements (LEs) | 504 | 504 | 504 | 336 | 336 | 208 |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 |
| Speed Grade | -4 | -4 | -3 (slower) | -4 | -4 | -4 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Terminal Finish | Lead-free (RoHS) | SnPb (non-RoHS) | [DATA_NEEDED] | Lead-free (RoHS) | SnPb (non-RoHS) | Lead-free (RoHS) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Approx. Unit Price (qty 1) | $12.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest density in the FLEX 8000 PLCC-84 family (vs EPF8452ALC84-4N)
- Lead-free RoHS-compliant terminal finish (vs EPF8636ALC84-4)
- Speed grade -4 (faster than -3) at same price (vs EPF8636ALC84-3)
- In-system reconfigurability via Altera EPC series PROMs (vs Antifuse FPGAs of the same era)
Design Notes
The EPF8636ALC84-4N operates at 5.0 V VCC and requires careful decoupling on every supply pin. Place a 0.1 Β΅F ceramic decoupling capacitor as close as possible to each VCC pin (pins 3, 17, 27, 37, 47, 57, 74), and add a 1-10 Β΅F bulk tantalum or ceramic capacitor per supply bank. Estimated: at typical 5 V VCCIO operation with ~50 mA quiescent current, total power dissipation is approximately 250 mW for a quiescent (unconfigured) device; configured device power scales with toggle rate and can reach 1 W. Plan thermal headroom accordingly.
The 84-pin PLCC J-Lead package has a 1.27 mm pitch and is best used with a PLCC-84 socket to simplify configuration swap, factory programming, and field replacement. If socketing is not used, ensure the J-leads are soldered with a profiled reflow or wave-solder cycle and that pad geometry matches the IPC-SM-782 land pattern. Maintain a continuous ground plane beneath the device to minimize ground bounce on the 63 LAB outputs and to provide low-impedance return paths for the 68 user I/Os.
Common pitfalls: (1) selecting the wrong configuration PROM - the EPC1064 stores 64 Kbit and is the minimum, but always verify against your compiled bitstream size; (2) omitting the external 1 kΞ© pull-up on nCONFIG and 10 kΞ© pull-up on nSTATUS - both pins require pull-ups for proper configuration sequencing; (3) confusing 5 V VCC with 3.3 V VCC - this device does NOT support 3.3 V operation and will be damaged by undervoltage; (4) using the -4 suffix when the -3 timing grade is required - the -4 is faster, so substituting the wrong grade will not fail but timing may close poorly; (5) failing to enable JTAG chain integrity test before deployment.
Place configuration-related components (EPC1064/EPC1441 PROM, JTAG header, nCONFIG pull-up, DCLK series-termination) within 50 mm of the FPGA to avoid signal-integrity issues on the configuration bus. Route CONF_DONE and nSTATUS away from high-frequency switching I/O to prevent false configuration errors. For designs that use MultiVolt I/O interfaces, group 5 V and 3.3 V I/O into separate banks (banks 1-4 on the EPF8636A) and add bus-switch or level-translator ICs at bank boundaries.
Compliance Information
The trailing 'N' suffix indicates lead-free, RoHS-compliant terminal finish per Altera ordering guide. FLEX 8000 family was never AEC-Q100 qualified - for automotive designs, choose MAX V or Cyclone IV. Conflict-minerals status compliant per Altera/Intel CMRT filings.
