EPM570T144A5N - MAX II CPLD, 570 LE, 144-TQFP | Altera (Intel)
MPN: EPM570T144A5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.77 | $42.77 |
| 10 | $38.5 | $385.00 |
| 100 | $32.1 | $3,210.00 |
| 500 | $26.45 | $13,225.00 |
| 1,000 | $22.8 | $22,800.00 |
Drop-in alternatives for EPM570T144A5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPM570T144A5N Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device | EPM570 |
| Logic Elements (LE) | 570 |
| Macro Cells | 440 |
| Maximum Operating Frequency | 201.1 MHz |
| Propagation Delay (tPD) | 5.4 ns |
| Process Technology | 0.18 Β΅m |
| Core Voltage | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage) |
| User I/O Pins | 144 |
| User Flash Memory (UFM) | 8 Kbits |
| Package | 144-pin TQFP (T144) |
| Mounting Type | Surface Mount |
| Operating Temperature Grade | Automotive (-40 Β°C to +125 Β°C) |
| Programming Interface | JTAG (IEEE 1149.1) / In-System Programmable |
| Configuration Memory | Internal Flash (non-volatile, instant-on) |
| RoHS Status | Compliant |
EPM570T144A5N Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (bank 1) |
| Pin 2 | I/O β General-purpose user I/O (bank 1) |
| Pin 3 | I/O β General-purpose user I/O (bank 1) |
| Pin 4 | I/O β General-purpose user I/O (bank 1) |
| Pin 5 | I/O β General-purpose user I/O (bank 1) |
| Pin 6 | I/O β General-purpose user I/O (bank 1) |
| Pin 7 | I/O β General-purpose user I/O (bank 1) |
| Pin 8 | I/O β General-purpose user I/O (bank 1) |
| Pin 9 | I/O β General-purpose user I/O (bank 1) |
| Pin 10 | I/O β General-purpose user I/O (bank 1) |
| Pin 11 | I/O β General-purpose user I/O (bank 1) |
| Pin 12 | I/O β General-purpose user I/O (bank 1) |
| Pin 13 | GND β Ground reference |
| Pin 14 | I/O β General-purpose user I/O (bank 1) |
| Pin 15 | I/O β General-purpose user I/O (bank 1) |
| Pin 16 | I/O β General-purpose user I/O (bank 1) |
| Pin 17 | I/O β General-purpose user I/O (bank 1) |
| Pin 18 | I/O β General-purpose user I/O (bank 1) |
| Pin 19 | I/O β General-purpose user I/O (bank 1) |
| Pin 20 | I/O β General-purpose user I/O (bank 1) |
| Pin 21 | I/O β General-purpose user I/O (bank 1) |
| Pin 22 | I/O β General-purpose user I/O (bank 1) |
| Pin 23 | I/O β General-purpose user I/O (bank 1) |
| Pin 24 | I/O β General-purpose user I/O (bank 1) |
| Pin 25 | I/O β General-purpose user I/O (bank 1) |
| Pin 26 | I/O β General-purpose user I/O (bank 1) |
| Pin 27 | I/O β General-purpose user I/O (bank 1) |
| Pin 28 | I/O β General-purpose user I/O (bank 1) |
| Pin 29 | I/O β General-purpose user I/O (bank 1) |
| Pin 30 | I/O β General-purpose user I/O (bank 1) |
| Pin 31 | I/O β General-purpose user I/O (bank 1) |
| Pin 32 | I/O β General-purpose user I/O (bank 1) |
| Pin 33 | I/O β General-purpose user I/O (bank 1) |
| Pin 34 | I/O β General-purpose user I/O (bank 1) |
| Pin 35 | I/O β General-purpose user I/O (bank 1) |
| Pin 36 | I/O β General-purpose user I/O (bank 1) |
| Pin 37 | GND β Ground reference |
| Pin 38 | VCCINT1 β Core supply (1.8 V) |
| Pin 39 | I/O β General-purpose user I/O (bank 1) |
| Pin 40 | I/O β General-purpose user I/O (bank 1) |
| Pin 41 | I/O β General-purpose user I/O (bank 1) |
| Pin 42 | I/O β General-purpose user I/O (bank 1) |
| Pin 43 | I/O β General-purpose user I/O (bank 1) |
| Pin 44 | I/O β General-purpose user I/O (bank 1) |
| Pin 45 | I/O β General-purpose user I/O (bank 1) |
| Pin 46 | I/O β General-purpose user I/O (bank 1) |
| Pin 47 | I/O β General-purpose user I/O (bank 1) |
| Pin 48 | I/O β General-purpose user I/O (bank 1) |
| Pin 49 | I/O β General-purpose user I/O (bank 1) |
| Pin 50 | I/O β General-purpose user I/O (bank 1) |
| Pin 51 | I/O β General-purpose user I/O (bank 1) |
| Pin 52 | I/O β General-purpose user I/O (bank 1) |
| Pin 53 | I/O β General-purpose user I/O (bank 1) |
| Pin 54 | I/O β General-purpose user I/O (bank 1) |
| Pin 55 | I/O β General-purpose user I/O (bank 1) |
| Pin 56 | I/O β General-purpose user I/O (bank 1) |
| Pin 57 | I/O β General-purpose user I/O (bank 1) |
| Pin 58 | I/O β General-purpose user I/O (bank 1) |
| Pin 59 | I/O β General-purpose user I/O (bank 1) |
| Pin 60 | I/O β General-purpose user I/O (bank 1) |
| Pin 61 | GND β Ground reference |
| Pin 62 | VCCIO1 β I/O supply for bank 1 (1.5/1.8/2.5/3.3 V) |
| Pin 63 | I/O β General-purpose user I/O (bank 2) |
| Pin 64 | I/O β General-purpose user I/O (bank 2) |
| Pin 65 | I/O β General-purpose user I/O (bank 2) |
| Pin 66 | I/O β General-purpose user I/O (bank 2) |
| Pin 67 | I/O β General-purpose user I/O (bank 2) |
| Pin 68 | I/O β General-purpose user I/O (bank 2) |
| Pin 69 | I/O β General-purpose user I/O (bank 2) |
| Pin 70 | I/O β General-purpose user I/O (bank 2) |
| Pin 71 | I/O β General-purpose user I/O (bank 2) |
| Pin 72 | I/O β General-purpose user I/O (bank 2) |
| Pin 73 | I/O β General-purpose user I/O (bank 2) |
| Pin 74 | I/O β General-purpose user I/O (bank 2) |
| Pin 75 | I/O β General-purpose user I/O (bank 2) |
| Pin 76 | I/O β General-purpose user I/O (bank 2) |
| Pin 77 | I/O β General-purpose user I/O (bank 2) |
| Pin 78 | I/O β General-purpose user I/O (bank 2) |
| Pin 79 | I/O β General-purpose user I/O (bank 2) |
| Pin 80 | I/O β General-purpose user I/O (bank 2) |
| Pin 81 | I/O β General-purpose user I/O (bank 2) |
| Pin 82 | I/O β General-purpose user I/O (bank 2) |
| Pin 83 | I/O β General-purpose user I/O (bank 2) |
| Pin 84 | I/O β General-purpose user I/O (bank 2) |
| Pin 85 | I/O β General-purpose user I/O (bank 2) |
| Pin 86 | I/O β General-purpose user I/O (bank 2) |
| Pin 87 | I/O β General-purpose user I/O (bank 2) |
| Pin 88 | I/O β General-purpose user I/O (bank 2) |
| Pin 89 | I/O β General-purpose user I/O (bank 2) |
| Pin 90 | I/O β General-purpose user I/O (bank 2) |
| Pin 91 | I/O β General-purpose user I/O (bank 2) |
| Pin 92 | I/O β General-purpose user I/O (bank 2) |
| Pin 93 | I/O β General-purpose user I/O (bank 2) |
| Pin 94 | I/O β General-purpose user I/O (bank 2) |
| Pin 95 | I/O β General-purpose user I/O (bank 2) |
| Pin 96 | I/O β General-purpose user I/O (bank 2) |
| Pin 97 | I/O β General-purpose user I/O (bank 2) |
| Pin 98 | I/O β General-purpose user I/O (bank 2) |
| Pin 99 | I/O β General-purpose user I/O (bank 2) |
| Pin 100 | I/O β General-purpose user I/O (bank 2) |
| Pin 101 | I/O β General-purpose user I/O (bank 2) |
| Pin 102 | I/O β General-purpose user I/O (bank 2) |
| Pin 103 | I/O β General-purpose user I/O (bank 2) |
| Pin 104 | I/O β General-purpose user I/O (bank 2) |
| Pin 105 | I/O β General-purpose user I/O (bank 2) |
| Pin 106 | I/O β General-purpose user I/O (bank 2) |
| Pin 107 | I/O β General-purpose user I/O (bank 2) |
| Pin 108 | I/O β General-purpose user I/O (bank 2) |
| Pin 109 | VCCINT2 β Core supply (1.8 V) |
| Pin 110 | GND β Ground reference |
| Pin 111 | I/O β General-purpose user I/O (bank 3) |
| Pin 112 | I/O β General-purpose user I/O (bank 3) |
| Pin 113 | I/O β General-purpose user I/O (bank 3) |
| Pin 114 | I/O β General-purpose user I/O (bank 3) |
| Pin 115 | I/O β General-purpose user I/O (bank 3) |
| Pin 116 | I/O β General-purpose user I/O (bank 3) |
| Pin 117 | I/O β General-purpose user I/O (bank 3) |
| Pin 118 | I/O β General-purpose user I/O (bank 3) |
| Pin 119 | I/O β General-purpose user I/O (bank 3) |
| Pin 120 | I/O β General-purpose user I/O (bank 3) |
| Pin 121 | I/O β General-purpose user I/O (bank 3) |
| Pin 122 | TDI β JTAG Test Data In |
| Pin 123 | TMS β JTAG Test Mode Select |
| Pin 124 | TCK β JTAG Test Clock |
| Pin 125 | TDO β JTAG Test Data Out |
| Pin 126 | nCE β Chip Enable (active low) |
| Pin 127 | nCONFIG β Configuration control (active low) |
| Pin 128 | CONF_DONE β Configuration Done status (open-drain) |
| Pin 129 | nSTATUS β Configuration status (active low) |
| Pin 130 | VCCIO3 β I/O supply for bank 3 (1.5/1.8/2.5/3.3 V) |
| Pin 131 | GND β Ground reference |
| Pin 132 | I/O β General-purpose user I/O (bank 3) |
| Pin 133 | I/O β General-purpose user I/O (bank 3) |
| Pin 134 | I/O β General-purpose user I/O (bank 3) |
| Pin 135 | I/O β General-purpose user I/O (bank 3) |
| Pin 136 | I/O β General-purpose user I/O (bank 3) |
| Pin 137 | I/O β General-purpose user I/O (bank 3) |
| Pin 138 | I/O β General-purpose user I/O (bank 3) |
| Pin 139 | I/O β General-purpose user I/O (bank 3) |
| Pin 140 | I/O β General-purpose user I/O (bank 3) |
| Pin 141 | I/O β General-purpose user I/O (bank 3) |
| Pin 142 | I/O β General-purpose user I/O (bank 3) |
| Pin 143 | I/O β General-purpose user I/O (bank 3) |
| Pin 144 | I/O β General-purpose user I/O (bank 3) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144A5N is suitable for 7 applications: Bus Interface Bridging, Power-Up Power-Rail Sequencing, Address Decoding and Chip-Select Generation, I/O Expansion for Microcontrollers, LED Display and Signage Drivers, Automotive Body and Chassis Modules, Industrial Control and Protocol Glue Logic.
Bus Interface Bridging
The EPM570T144A5N is well suited to bridge mismatched bus widths and voltages between microcontrollers, ASICs, and ASSPs. Its 144 user I/O pins can simultaneously drive a 32-bit local bus and a 16-bit peripheral bus, while multi-voltage VCCIO banks (1.5/1.8/2.5/3.3 V) eliminate external level shifters when connecting to legacy 5 V-tolerant or modern 1.8 V cores. The 5.4 ns pin-to-pin delay supports bus cycles up to ~150 MHz, matching common SDRAM and asynchronous SRAM timings. Place the CPLD between the host processor and the peripheral, route JTAG to a header for in-system programming, and use one global clock pin for synchronous bus operations.
Recommended
Power-Up Power-Rail Sequencing
Deterministic power-rail sequencing is a classic CPLD use case, and the EPM570T144A5N fits this role with 144 I/O pins that can each control a discrete enable line, and a Flash-based instant-on configuration that begins sequencing within microseconds of VCCINT ramp. Each macro cell can implement a programmable delay timer, allowing the designer to chain enables for FPGA cores, ASICs, DDR memory, and analog subsystems. The 5.4 ns propagation delay is more than fast enough for sequencing tasks where delays are typically measured in milliseconds. Tie all unused I/O to defined logic levels to avoid floating pins during the early power-on window, and place 0.1 uF decoupling capacitors adjacent to each VCCIO pin pair.
Recommended
Address Decoding and Chip-Select Generation
Address decoding for memory maps and chip-select generation is the original use case for the MAX II CPLD family, and the EPM570T144A5N provides 440 macro cells and 144 I/O to decode wide address buses with combinatorial logic. The device supports fast propagation paths that produce chip-select outputs in a single logic level, ensuring zero wait-state access for memory-mapped peripherals. Its non-volatile Flash configuration means the decoded map is available before any CPU boot ROM executes, simplifying system bring-up. Configure the design in Quartus Prime using schematic entry or VHDL, and verify timing with the TimeQuest timing analyzer.
Recommended
I/O Expansion for Microcontrollers
Many low-pin-count microcontrollers need additional GPIOs for keypads, LCDs, LEDs, or sensor arrays, and the EPM570T144A5N serves as an I/O expander controlled over SPI or I2C by the host MCU. Each macro cell can be configured as an input, output, or bidirectional pin with programmable pull-up, slew rate, and drive strength. The 201.1 MHz maximum internal frequency supports high-speed SPI peripherals up to 50 MHz. Using a CPLD rather than a discrete I/O expander IC keeps the pinout flexible - designers can change the number of GPIOs and pin assignments without respinning the host PCB, by simply re-programming the Flash.
Recommended
LED Display and Signage Drivers
The EPM570T144A5N's 144 user I/O and 440 macro cells make it suitable for driving multi-segment LED displays, dot-matrix panels, and DMX-controlled signage. Each macro cell can implement a PWM dimming channel, and the 201.1 MHz internal frequency allows smooth 16-bit PWM at refresh rates above 1 kHz with no visible flicker. Multi-voltage I/O supports both 3.3 V logic-level LEDs and 5 V high-brightness strings. Use the on-chip 8 Kbit User Flash Memory (UFM) to store display fonts, animation frames, or gamma correction tables, accessed via the same JTAG port used for configuration.
Recommended
Automotive Body and Chassis Modules
The 'A' suffix in EPM570T144A5N denotes the automotive temperature grade (-40 Β°C to +125 Β°C), qualifying it for body controllers, gateway modules, instrument cluster logic, and chassis domain controllers. With 144 I/O pins, the device can interface directly to CAN/LIN transceivers, discrete switches, relay drivers, and H-bridge motor pre-drivers. Instant-on Flash configuration ensures the module is operational within microseconds of ignition, a hard requirement for airbag and ABS subsystems. AEC-Q100 qualification is typically inherited at the module level when this part is specified into automotive ECU designs.
Recommended
Industrial Control and Protocol Glue Logic
In industrial PLCs, motion controllers, and process automation modules, the EPM570T144A5N provides the glue logic that ties microcontrollers, FPGAs, ADCs, and motor pre-drivers together. Industrial protocols such as Modbus RTU, RS-485 half-duplex direction control, SPI-to-parallel ADC interfacing, and quadrature encoder decoding all fit easily within 440 macro cells. The automotive temperature grade gives extra margin for cabinet-mounted equipment that may see elevated ambient temperatures near motors or heaters. JTAG-based in-system programming supports field firmware updates via the same programming port used in production.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144A5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT144I5N | EPM570GT144C5N | EPM570GF256C5N | EPM570F256C5N | EPM570GM256C5N | EPM570T100A5N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | FBGA-256 - different package | FBGA-256 - different package | MBGA-256 - different package | TQFP-100 - smaller footprint |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 | 570 |
| Macro Cells | 440 | 440 | 440 | 440 | 440 | 440 | 440 |
| Propagation Delay (tPD) | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns |
| Temperature Grade | Automotive (-40 to +125 C) | Industrial (-40 to +100 C) | Commercial (0 to +85 C) | Commercial (0 to +85 C) | Commercial (0 to +85 C) | Commercial (0 to +85 C) | Automotive (-40 to +125 C) |
| User I/O Count | 144 | 144 | 144 | 160 | 160 | 160 | 76 |
| Process Technology | 0.18 um | 0.18 um | 0.18 um | 0.18 um | 0.18 um | 0.18 um | 0.18 um |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Configuration Memory | Internal Flash (non-volatile) | Internal Flash (non-volatile) | Internal Flash (non-volatile) | Internal Flash (non-volatile) | Internal Flash (non-volatile) | Internal Flash (non-volatile) | Internal Flash (non-volatile) |
Key Differentiators
- Largest I/O count in the MAX II CPLD family (vs EPM570T100A5N)
- Automotive temperature grade qualification (vs EPM570GT144I5N)
- Non-volatile Flash configuration (vs SRAM-based FPGA)
- Lowest-power CPLD option in this density class (vs EPM570M256C5N)
Design Notes
The EPM570T144A5N requires two separate supplies: VCCINT (1.8 V typical) for the core logic and VCCIO (1.5 V, 1.8 V, 2.5 V, or 3.3 V per bank) for the I/O banks. Per the MAX II datasheet power-supply recommendations, place one 0.1 uF decoupling capacitor adjacent to every VCCINT and VCCIO pin pair, plus a bulk 10-47 uF tantalum or ceramic capacitor near each supply rail entry point. Power-on reset (POR) requires both rails to ramp monotonically within datasheet-specified rise times; failure to do so can result in partial Flash configuration and unreliable JTAG access.
The 144-pin TQFP package has 0.5 mm pitch leads and benefits from a 4-layer PCB with a continuous ground plane on the layer directly beneath the device. Route all JTAG signals (TDI, TMS, TCK, TDO) with controlled impedance and keep their total length under 100 mm to avoid signal integrity issues during in-system programming. The exposed thermal pad on the bottom of the TQFP should be soldered to a copper pour connected to GND for best thermal performance.
Multi-voltage I/O banks on the EPM570T144A5N can be configured independently to 1.5/1.8/2.5/3.3 V, allowing direct interface to mixed-voltage buses without external level shifters. However, each bank must use a single VCCIO level - mixing voltages within one bank is not allowed. According to the MAX II datasheet, unused I/O pins should be configured as outputs driving GND or as inputs with the internal weak pull-up enabled to avoid floating-pin supply leakage.
Do not confuse the EPM570 (570 LE, MAX II family) with the older EPM5128, EPM5192, or EPM5064 parts from the classic MAX family - they use different programming files and JTAG instructions, and are not pin-compatible. Also avoid mixing up the EPM570T144A5N (TQFP-144, automotive) with the EPM570F256 (FBGA-256) or EPM570M100 (TQFP-100) variants - the package, pinout, and Quartus pin-assignment files all differ.
Place the JTAG connector or test-points within 50 mm of the EPM570T144A5N package to support USB-Blaster programming in production. Add 4.7 kohm pull-up resistors on TMS, TDI, and nCONFIG per the MAX II JTAG configuration guidelines, and place a 10 kohm pull-up on nSTATUS and CONF_DONE (both are open-drain). For multi-device JTAG chains, daisy-chain TDI to TDO with a 4.7 kohm pull-up on the final TDO.
Compliance Information
RoHS and REACH compliance per Altera/Intel product declarations. Lead-free (Pb-free) reflow profile per JEDEC J-STD-020. AEC-Q100 is not explicitly stated for this part - the 'A' suffix indicates automotive temperature grade only. Halogen-free status was not listed in the verified web data.
