EPM570T144C5 - 440-Macrocell MAX II CPLD, 5.4ns, 144-TQFP | Intel
MPN: EPM570T144C5 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $27.01 | $27.01 |
| 10 | $24.3 | $243.00 |
| 100 | $21.6 | $2,160.00 |
| 500 | $19.45 | $9,725.00 |
| 1,000 | $17.3 | $17,300.00 |
Drop-in alternatives for EPM570T144C5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570T144C4N
✅ Drop-In✓ In Stock
$25.1 / Unit
View Datasheet →EPM570T144C4
✅ Drop-In✓ In Stock
$19.2 / Unit
View Datasheet →EPM570T144C3N
✅ Drop-In✓ In Stock
$9.6 / Unit
View Datasheet →EPM570T144C3
✅ Drop-In✓ In Stock
$27.4 / Unit
View Datasheet →EPM570T144A5N
✅ Drop-In✓ In Stock
$22.8 / Unit
View Datasheet →EPM570GT144C5N
✅ Drop-In✓ In Stock
$14.2 / Unit
View Datasheet →EPM570GT144C5
✅ Drop-In✓ In Stock
$14.2 / Unit
View Datasheet →EPM570GT144C4N
✅ Drop-In✓ In Stock
$22.5 / Unit
View Datasheet →EPM570T144C5 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 440 |
| Pin-to-Pin Delay (tPD) | 5.4 ns |
| Maximum Internal Frequency | 201.1 MHz |
| User I/Os | 116 |
| Total Package Pins | 144 |
| Package / Case | 144-TQFP (TQFP-144) |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (multi-voltage I/O supported) |
| Configuration Memory | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1), ISP |
| Process Technology | 0.18 µm CMOS |
| Operating Temperature | Commercial (0 °C to +85 °C) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
EPM570T144C5 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | GND — Ground |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | I/O — User I/O pin (bank 1) |
| Pin 16 | I/O — User I/O pin (bank 1) |
| Pin 17 | I/O — User I/O pin (bank 1) |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | I/O — User I/O pin (bank 2) |
| Pin 20 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 21 | I/O — User I/O pin (bank 2) |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | I/O — User I/O pin (bank 2) |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | I/O — User I/O pin (bank 2) |
| Pin 26 | I/O — User I/O pin (bank 2) |
| Pin 27 | I/O — User I/O pin (bank 2) |
| Pin 28 | GND — Ground |
| Pin 29 | I/O — User I/O pin (bank 2) |
| Pin 30 | I/O — User I/O pin (bank 2) |
| Pin 31 | I/O — User I/O pin (bank 2) |
| Pin 32 | I/O — User I/O pin (bank 2) |
| Pin 33 | I/O — User I/O pin (bank 2) |
| Pin 34 | I/O — User I/O pin (bank 2) |
| Pin 35 | I/O — User I/O pin (bank 2) |
| Pin 36 | I/O — User I/O pin (bank 2) |
| Pin 37 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 38 | I/O — User I/O pin (bank 2) |
| Pin 39 | I/O — User I/O pin (bank 3) |
| Pin 40 | I/O — User I/O pin (bank 3) |
| Pin 41 | GND — Ground |
| Pin 42 | I/O — User I/O pin (bank 3) |
| Pin 43 | I/O — User I/O pin (bank 3) |
| Pin 44 | I/O — User I/O pin (bank 3) |
| Pin 45 | I/O — User I/O pin (bank 3) |
| Pin 46 | I/O — User I/O pin (bank 3) |
| Pin 47 | I/O — User I/O pin (bank 3) |
| Pin 48 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 49 | I/O — User I/O pin (bank 3) |
| Pin 50 | I/O — User I/O pin (bank 3) |
| Pin 51 | I/O — User I/O pin (bank 3) |
| Pin 52 | I/O — User I/O pin (bank 3) |
| Pin 53 | I/O — User I/O pin (bank 3) |
| Pin 54 | I/O — User I/O pin (bank 3) |
| Pin 55 | I/O — User I/O pin (bank 3) |
| Pin 56 | GND — Ground |
| Pin 57 | I/O — User I/O pin (bank 3) |
| Pin 58 | I/O — User I/O pin (bank 3) |
| Pin 59 | I/O — User I/O pin (bank 3) |
| Pin 60 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 61 | I/O — User I/O pin (bank 4) |
| Pin 62 | I/O — User I/O pin (bank 4) |
| Pin 63 | I/O — User I/O pin (bank 4) |
| Pin 64 | I/O — User I/O pin (bank 4) |
| Pin 65 | I/O — User I/O pin (bank 4) |
| Pin 66 | I/O — User I/O pin (bank 4) |
| Pin 67 | I/O — User I/O pin (bank 4) |
| Pin 68 | GND — Ground |
| Pin 69 | I/O — User I/O pin (bank 4) |
| Pin 70 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 71 | I/O — User I/O pin (bank 4) |
| Pin 72 | I/O — User I/O pin (bank 4) |
| Pin 73 | I/O — User I/O pin (bank 4) |
| Pin 74 | I/O — User I/O pin (bank 4) |
| Pin 75 | I/O — User I/O pin (bank 4) |
| Pin 76 | I/O — User I/O pin (bank 4) |
| Pin 77 | I/O — User I/O pin (bank 4) |
| Pin 78 | I/O — User I/O pin (bank 4) |
| Pin 79 | GND — Ground |
| Pin 80 | I/O — User I/O pin (bank 4) |
| Pin 81 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 82 | I/O — User I/O pin (bank 4) |
| Pin 83 | I/O — User I/O pin (bank 4) |
| Pin 84 | I/O — User I/O pin (bank 4) |
| Pin 85 | I/O — User I/O pin (bank 4) |
| Pin 86 | I/O — User I/O pin (bank 4) |
| Pin 87 | I/O — User I/O pin (bank 4) |
| Pin 88 | TDI — JTAG Test Data In |
| Pin 89 | TMS — JTAG Test Mode Select |
| Pin 90 | TCK — JTAG Test Clock |
| Pin 91 | GND — Ground |
| Pin 92 | VCCINT — Core supply voltage (1.8 V typical) |
| Pin 93 | I/O — User I/O pin (bank 4) |
| Pin 94 | I/O — User I/O pin (bank 4) |
| Pin 95 | I/O — User I/O pin (bank 4) |
| Pin 96 | I/O — User I/O pin (bank 4) |
| Pin 97 | I/O — User I/O pin (bank 1) |
| Pin 98 | I/O — User I/O pin (bank 1) |
| Pin 99 | GND — Ground |
| Pin 100 | I/O — User I/O pin (bank 1) |
| Pin 101 | I/O — User I/O pin (bank 1) |
| Pin 102 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 103 | I/O — User I/O pin (bank 1) |
| Pin 104 | I/O — User I/O pin (bank 1) |
| Pin 105 | I/O — User I/O pin (bank 1) |
| Pin 106 | I/O — User I/O pin (bank 1) |
| Pin 107 | I/O — User I/O pin (bank 1) |
| Pin 108 | I/O — User I/O pin (bank 1) |
| Pin 109 | I/O — User I/O pin (bank 1) |
| Pin 110 | I/O — User I/O pin (bank 1) |
| Pin 111 | GND — Ground |
| Pin 112 | I/O — User I/O pin (bank 1) |
| Pin 113 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 114 | I/O — User I/O pin (bank 1) |
| Pin 115 | I/O — User I/O pin (bank 1) |
| Pin 116 | I/O — User I/O pin (bank 1) |
| Pin 117 | I/O — User I/O pin (bank 1) |
| Pin 118 | I/O — User I/O pin (bank 1) |
| Pin 119 | I/O — User I/O pin (bank 1) |
| Pin 120 | I/O — User I/O pin (bank 1) |
| Pin 121 | I/O — User I/O pin (bank 1) |
| Pin 122 | GND — Ground |
| Pin 123 | I/O — User I/O pin (bank 1) |
| Pin 124 | TDO — JTAG Test Data Out |
| Pin 125 | I/O — User I/O pin (bank 1) |
| Pin 126 | VCCINT — Core supply voltage (1.8 V typical) |
| Pin 127 | I/O — User I/O pin (bank 1) |
| Pin 128 | I/O — User I/O pin (bank 1) |
| Pin 129 | I/O — User I/O pin (bank 1) |
| Pin 130 | I/O — User I/O pin (bank 1) |
| Pin 131 | I/O — User I/O pin (bank 1) |
| Pin 132 | I/O — User I/O pin (bank 1) |
| Pin 133 | I/O — User I/O pin (bank 1) |
| Pin 134 | GND — Ground |
| Pin 135 | I/O — User I/O pin (bank 1) |
| Pin 136 | I/O — User I/O pin (bank 1) |
| Pin 137 | I/O — User I/O pin (bank 1) |
| Pin 138 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 139 | I/O — User I/O pin (bank 1) |
| Pin 140 | I/O — User I/O pin (bank 1) |
| Pin 141 | I/O — User I/O pin (bank 1) |
| Pin 142 | I/O — User I/O pin (bank 1) |
| Pin 143 | I/O — User I/O pin (bank 1) |
| Pin 144 | I/O — User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144C5 is suitable for 7 applications: Bus Bridging and Voltage Translation, I/O Expansion for Microcontrollers, Power Sequencing and Reset Distribution, Address Decoding and Chip-Select Generation, Industrial Control and Factory Automation, Consumer Electronics and Display Driving, Communications Equipment Glue Logic.
Bus Bridging and Voltage Translation
The EPM570T144C5 is well-suited to bus-bridging and voltage-level translation between mismatched logic domains because of its 116 user I/Os and multi-voltage I/O bank support (1.5/1.8/2.5/3.3 V). Its 5.4 ns pin-to-pin delay comfortably handles PCI, local-bus, and asynchronous memory interfaces without metastability risk. Placed between a 3.3 V microcontroller and 1.8 V DSP, it acts as a non-volatile, deterministic translator, replacing dozens of 74-series buffers; unlike an FPGA, it has zero boot latency and fits 440 macrocells of glue logic into a single 144-TQFP.
Recommended
I/O Expansion for Microcontrollers
The EPM570T144C5 expands GPIO-limited microcontrollers by adding up to 116 user I/Os with JTAG-reprogrammable routing, ideal when the host MCU has insufficient pins for keypads, LEDs, and peripheral strobes. Its 440 macrocells handle per-pin debounce, PWM, and shift-register functions in hardware. Powered from a 2.5 V rail, the device complements 3.3 V MCUs by offloading real-time I/O tasks with deterministic 5.4 ns latency, freeing the MCU CPU for higher-level application code.
Recommended
Power Sequencing and Reset Distribution
The EPM570T144C5 generates and distributes multi-rail power-up/power-down sequencing for systems with strict rail-order requirements (e.g., processors requiring core-before-I/O). Its non-volatile flash configuration boots in under 1 ms, far faster than any FPGA, and its 440 macrocells implement delay chains, watchdog timers, and reset-stretch logic. Typical use: sequencing a 1.0 V core, 1.8 V DDR, and 3.3 V I/O with individually programmable delay and fault handling.
Recommended
Address Decoding and Chip-Select Generation
The EPM570T144C5 replaces legacy 74-series address-decoder trees with a single 144-TQFP CPLD, generating up to 8-12 qualified chip-selects from a host address bus. Its 5.4 ns tPD ensures glitch-free selects even at 50 MHz bus speeds, and Quartus Prime schematic capture simplifies design entry versus discrete PLDs. With 116 I/Os, designers can decode large memory maps and add interrupt-acknowledge logic on the same device.
Recommended
Industrial Control and Factory Automation
The EPM570T144C5 drives digital I/O in PLCs, motor-control interfaces, and factory-automation backplanes thanks to its 116 I/Os and configurable logic blocks for state machines, encoder counters, and safety interlocks. Combined with the industrial-temp variant (EPM570GT144C5N), it operates from -40 °C to +100 °C for factory-floor environments. The 0.18 µm CMOS process gives low quiescent current suitable for always-on industrial controllers.
Recommended
Consumer Electronics and Display Driving
The EPM570T144C5 is used in consumer electronics for LED matrix driving, LCD timing control, button scanning, and IR-protocol decoding on cost-sensitive mainboards. Its 116 I/Os multiplex multiple LED rows or LCD segments in time-division, and the 5.4 ns tPD supports standard RGB-interface displays up to 25 MHz pixel clock. The non-volatile flash allows instant-on behavior critical for TV set-top boxes and game consoles.
Recommended
Communications Equipment Glue Logic
In routers, switches, and wireless base stations, the EPM570T144C5 acts as glue logic between network processors, PHYs, and SERDES devices, generating frame-sync pulses, LED status indicators, and watchdog strobes. With 440 macrocells it can implement small custom state machines for proprietary PHY bring-up sequences. Multi-voltage I/O support bridges 1.8 V SERDES, 2.5 V PHY, and 3.3 V management interfaces without external level shifters.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144C5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T144C4N | EPM570T144C3N | EPM570T144A5N | EPM570GT144C5N | EPM570GT144C5 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 144-TQFP | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same |
| Macro Cells | 440 | 440 | 440 | 440 | 440 | 440 |
| Pin-to-Pin Delay (tPD) | 5.4 ns | 4.5 ns (faster) | 3.3 ns (fastest) | 5.4 ns (same) | 5.4 ns (same) | 5.4 ns (same) |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 116 |
| Temperature Grade | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Automotive (-40 to +125 °C) | Industrial (-40 to +100 °C) | Industrial (-40 to +100 °C) |
| Lead-Free (Pb-Free) | No (C5 is SnPb; C5N is lead-free) | Yes (C4N suffix) | Yes (C3N suffix) | Yes (A5N suffix) | Yes (C5N suffix) | No |
| Configuration Memory | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) | On-chip flash (non-volatile) |
Key Differentiators
- Same-family speed-grade options in identical 144-TQFP pinout (vs EPM570T144C4N / EPM570T144C3N)
- Industrial temperature variant (EPM570GT144C5) for harsh environments (vs EPM570T144C5 (commercial))
- Automotive-grade variant (EPM570T144A5N) for AEC-Q100 designs (vs EPM570T144C5 (commercial))
Design Notes
Estimated: The EPM570T144C5 requires VCCINT (core, 1.8 V typical) and VCCIO (I/O banks, 1.5/1.8/2.5/3.3 V) rails. Each VCCIO bank can run independently for mixed-voltage I/O. Decouple each VCCIO/VCCINT pin with a 0.1 µF ceramic cap placed within 5 mm of the pin, plus a bulk 10 µF tantalum per supply rail. Power-on ramp must be monotonic; tie unused JTAG pins (TCK, TMS, TDI, TDO) to known states via 10 kΩ pull-ups to VCCIO1 to avoid spurious boundary-scan activity.
Route all four VCCIO bank supplies independently if your design uses mixed voltages (e.g., 3.3 V for bank 1, 1.8 V for bank 2). Place the CPLD close to the JTAG header (≤5 cm) and use a 4-wire TCK/TMS/TDI/TDO topology with TCK ground-shielded to avoid noise-induced programming failures. Leave pin 1 dot indicator visible for assembly orientation. Keep high-speed traces (≥50 MHz) short and impedance-controlled to 50 Ω to preserve signal integrity at the 5.4 ns tPD edge rate.
Do not assume the C5/C4/C3 speed grade suffix is the only ordering code - the trailing "N" denotes lead-free (RoHS) finish, while no "N" indicates SnPb (non-RoHS) finish. RoHS-compliant designs MUST order the C5N variant or equivalent. Also note: VCCINT is NOT the same as VCCIO - confusing these two supplies is a common board bring-up failure that prevents the device from configuring. Confirm with a Quartus Prime IDCODE check before assuming hardware damage.
Compliance Information
EPM570T144C5 (without 'N' suffix) is non-RoHS (SnPb finish). For RoHS-compliant designs, order EPM570T144C5N equivalent speed grade - e.g., EPM570T144C4N. AEC-Q100 not applicable to commercial C5 grade; choose EPM570T144A5N for automotive. Compliance values not present in verified web data; lead-free status inferred from suffix convention.
