EPM570T144-5 - MAX II CPLD 570 LE, 144-pin TQFP | Altera
MPN: EPM570T144-5 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16.5 | $16.50 |
| 10 | $14.85 | $148.50 |
| 100 | $12.95 | $1,295.00 |
| 500 | $11.2 | $5,600.00 |
| 1,000 | $9.85 | $9,850.00 |
Drop-in alternatives for EPM570T144-5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570T144C5N
✅ Drop-In✓ In Stock
$9.35 / Unit
View Datasheet →EPM570T144C4N
✅ Drop-In✓ In Stock
$25.1 / Unit
View Datasheet →EPM570T144A5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$22.8 / Unit
View Datasheet →EPM570GT144C5N
✅ Drop-In✓ In Stock
$14.2 / Unit
View Datasheet →LC4256ZE-5TN144C
✅ Drop-In📋 Reference alternative (not in catalog)
LC4128ZE-5TN144C
✅ Drop-In📋 Reference alternative (not in catalog)
EPM570T144-5 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device | EPM570 |
| Logic Elements (LE) | 570 |
| Macrocells (typical) | 440 |
| User I/O Pins | 116 |
| Package | TQFP-144 (T144) |
| Pin Count | 144 |
| Speed Grade | -5 (≈5.0 ns tPD1) |
| Process Technology | 0.18 µm |
| Non-volatile Configuration | Internal Flash (instant-on) |
| User Flash Memory (UFM) | 8 Kbits |
| I/O Banks | 4 |
| MultiVolt I/O Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| VCCINT | 3.3 V or 2.5 V (per bank group) |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) |
| RoHS Status | Depends on date code (pre-2010 lots non-RoHS; lead-free Pb-free opt. available) |
EPM570T144-5 Pin Configuration
| Pin 1 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 2 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 3 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 4 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 5 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 6 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 7 | VCCIO1 — Bank 1 I/O supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 8 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 9 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 10 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 13 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 14 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 15 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 16 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 17 | VCCINT — Core supply voltage (3.3 V or 2.5 V) |
| Pin 18 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 19 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 20 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 23 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 24 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 25 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 26 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 27 | VCCIO2 — Bank 2 I/O supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 28 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 29 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 30 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 31 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 32 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 35 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 36 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 37 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 38 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 39 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 40 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 41 | VCCINT — Core supply voltage (3.3 V or 2.5 V) |
| Pin 42 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 43 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 44 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 45 | GND — Ground |
| Pin 46 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 47 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 48 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 49 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 50 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 51 | VCCIO2 — Bank 2 I/O supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 52 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 53 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 54 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 55 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 56 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 57 | GND — Ground |
| Pin 58 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 59 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 60 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 61 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 62 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 63 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 64 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 65 | VCCINT — Core supply voltage (3.3 V or 2.5 V) |
| Pin 66 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 67 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 68 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 69 | GND — Ground |
| Pin 70 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 71 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 72 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 73 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 74 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 75 | VCCIO3 — Bank 3 I/O supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 76 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 77 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 78 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 79 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 80 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 81 | GND — Ground |
| Pin 82 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 83 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 84 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 85 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 86 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 87 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 88 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 89 | VCCINT — Core supply voltage (3.3 V or 2.5 V) |
| Pin 90 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 91 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 92 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 93 | GND — Ground |
| Pin 94 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 95 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 96 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 97 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 98 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 99 | VCCIO3 — Bank 3 I/O supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 100 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 101 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 102 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 103 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 104 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 105 | GND — Ground |
| Pin 106 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 107 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 108 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 109 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 110 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 111 | VCCIO4 — Bank 4 I/O supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 112 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 113 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 114 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 115 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 116 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 117 | GND — Ground |
| Pin 118 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 119 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 120 | TDI — JTAG Test Data In |
| Pin 121 | TMS — JTAG Test Mode Select |
| Pin 122 | TCK — JTAG Test Clock |
| Pin 123 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 124 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 125 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 126 | VCCINT — Core supply voltage (3.3 V or 2.5 V) |
| Pin 127 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 128 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 129 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 130 | GND — Ground |
| Pin 131 | nCONFIG — Configuration control (pull high for normal operation) |
| Pin 132 | nSTATUS — Configuration status output |
| Pin 133 | CONF_DONE — Configuration done indicator |
| Pin 134 | TDO — JTAG Test Data Out |
| Pin 135 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 136 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 137 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 138 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 139 | VCCIO4 — Bank 4 I/O supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 140 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 141 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 142 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 143 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 144 | I/O — General-purpose user I/O pin (Bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144-5 is suitable for 7 applications: 3.3 V / 2.5 V / 1.8 V Mixed-Voltage Bus Bridging, Microprocessor Glue Logic and Address Decoding, FPGA and ASIC I/O Expansion, Industrial Control and Factory Automation, Portable and Battery-Powered Devices, Reset Sequencer and Power Management Controller, LED Driving and Display Multiplexing.
3.3 V / 2.5 V / 1.8 V Mixed-Voltage Bus Bridging
The EPM570T144-5's 4 MultiVolt I/O banks (1.5/1.8/2.5/3.3 V per bank) make it a natural bus-bridging CPLD between legacy 3.3 V microcontrollers, 2.5 V memories and 1.8 V ASICs. Place the device between source and destination buses with each bank tied to its respective rail, eliminating discrete level-shifter ICs. The 116 user I/O pins provide 4 independent 8-16-bit bus interfaces, and tPD1 ≈5 ns keeps inter-bus latency under one 100 MHz clock. Quartus II pin-assignment software enforces MultiVolt rules automatically, reducing board complexity and BOM cost in mixed-voltage designs.
Recommended
Microprocessor Glue Logic and Address Decoding
The EPM570T144-5 is widely used as glue logic around microprocessors (8051, ARM Cortex-M, PowerPC, x86 southbridge) where it generates chip-selects, wait-state timing and interrupt steering. 570 logic elements comfortably implement address-decoder trees, custom peripherals and reset sequencers in a single chip. The instant-on non-volatile Flash configuration removes the boot-wait window that SRAM FPGAs introduce, letting the host CPU access memory on the first clock after POR. Pair the EPM570T144-5 with a 50 MHz or 100 MHz host bus and route JTAG to a header for in-system updates.
Recommended
FPGA and ASIC I/O Expansion
Use the EPM570T144-5 to expand the I/O count of an FPGA or ASIC whose high-speed serial transceivers leave insufficient LVCMOS pins for slow control signals (LEDs, switches, GPIO buses). The EPM570's 116 user I/O pins and deterministic 5 ns tPD make it ideal for low-frequency parallel buses, slow control logic and reset distribution. Designers connect the FPGA's general-purpose pins to the CPLD, then route the expanded bus to the board. The CPLD is in-system programmable via JTAG, allowing last-minute pinout changes without respinning the FPGA bitstream.
Recommended
Industrial Control and Factory Automation
The EPM570T144-5's deterministic timing, MultiVolt I/O and instant-on behaviour suit industrial control boards that interface 24 V PLC field buses, 5 V sensors and 3.3 V controllers. Place the device between the field-bus isolator and the MCU to implement debounce filters, watchdog timers and machine-safety logic. Industrial-grade temperature range options are available; the A5N automotive variant extends operation into harsher environments. Its 0.18 µm Flash process and rugged TQFP-144 package provide long-term reliability in factory environments.
Recommended
Portable and Battery-Powered Devices
In portable equipment (handheld instruments, battery-powered IoT nodes, mobile accessories), the EPM570T144-5's low standby current, instant-on Flash configuration and 2.5 V VCCINT option minimise battery drain during sleep and eliminate boot latency at wake-up. The UFM block can store user parameters (calibration constants, serial numbers, configuration profiles) without an external EEPROM. Pair the device with a low-power MCU and route JTAG to a test header for field-upgradeable firmware in the CPLD itself.
Recommended
Reset Sequencer and Power Management Controller
The EPM570T144-5 is commonly used as a board-level reset and power-sequencing controller in systems with multiple voltage rails (e.g., 1.0 V core, 1.8 V memory, 3.3 V I/O). The CPLD monitors each rail via voltage supervisors and asserts reset signals in a programmable sequence, ensuring MCUs and FPGAs come up in a deterministic order. The instant-on non-volatile configuration means the sequencer is active within microseconds of the first rail being valid - critical for hot-swap and inrush-control circuits. Use the UFM to store sequencing parameters and JTAG for field updates.
Recommended
LED Driving and Display Multiplexing
The EPM570T144-5's 116 user I/O and 5 ns tPD1 make it well suited to driving 7-segment or dot-matrix LED displays where the MCU lacks sufficient pins or PWM channels. Implement Charlieplexing, Charlie-plexed matrix scanning and software PWM dimming in the CPLD's logic array, freeing the host processor for higher-level tasks. The 4 MultiVolt I/O banks allow direct connection to common-cathode LED arrays without level shifting. Multiple display refresh rates and patterns can be stored in the 8 Kbit UFM block for instant recall.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144-5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T144C5N | EPM570T144C4N | EPM570T144A5N | EPM570GT144C5N | LC4256ZE-5TN144C | LC4128ZE-5TN144C |
|---|---|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Lattice Semiconductor | Lattice Semiconductor |
| Logic Elements / Macrocells | 570 LE / 440 macrocells | 570 LE / 440 macrocells | 570 LE / 440 macrocells | 570 LE / 440 macrocells | 570 LE / 440 macrocells | 256 macrocells | 128 macrocells |
| Speed Grade (tPD1) | -5 (≈5.0 ns) | -5 (≈5.0 ns) | -4 (≈4.0 ns, faster) | -5 (≈5.0 ns) | -5 (≈5.0 ns) | -5 (≈5.0 ns) | -5 (≈5.0 ns) |
| User I/O | 116 | 116 | 116 | 116 | 116 | 108 | 96 |
| VCCINT | 3.3 V or 2.5 V | 3.3 V or 2.5 V | 3.3 V or 2.5 V | 3.3 V or 2.5 V | 1.8 V (G-variant) | 1.8 V core | 1.8 V core |
| MultiVolt I/O Banks | 4 banks (1.5/1.8/2.5/3.3 V) | 4 banks (1.5/1.8/2.5/3.3 V) | 4 banks (1.5/1.8/2.5/3.3 V) | 4 banks (1.5/1.8/2.5/3.3 V) | 4 banks (1.5/1.8/2.5/3.3 V) | 4 banks | 4 banks |
| Non-volatile Configuration | Internal Flash (instant-on) | Internal Flash (instant-on) | Internal Flash (instant-on) | Internal Flash (instant-on) | Internal Flash (instant-on) | Internal Flash (instant-on) | Internal Flash (instant-on) |
| Programming Interface | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) |
| RoHS / Lead-free | Depends on date code | Yes (RoHS, Pb-free) | Yes (RoHS, Pb-free) | Yes (RoHS, Pb-free) | Yes (RoHS, Pb-free) | Yes (RoHS, Pb-free) | Yes (RoHS, Pb-free) |
Key Differentiators
- Industry's highest-density non-volatile CPLD in TQFP-144 (vs LC4256ZE-5TN144C)
- 8 Kbit on-chip User Flash Memory (vs LC4128ZE-5TN144C)
- MultiVolt core (3.3 V or 2.5 V) selectable (vs EPM570GT144C5N)
Design Notes
Decouple each VCCINT and VCCIO bank pin with a 0.1 µF ceramic capacitor placed within 5 mm of the supply pin, and add one bulk 10 µF tantalum or ceramic per bank group. According to Altera's MAX II Handbook, VCCINT must be 3.3 V or 2.5 V across all core pins (do NOT mix). VCCIO banks are independent; each can be set to 1.5/1.8/2.5/3.3 V to interface mixed-voltage logic without level shifters.
Route JTAG signals (TCK, TMS, TDI, TDO) as a daisy-chainable bus with 10 kΩ pull-ups on TCK, TMS and TDI to keep the TAP controller in a benign state during board reset. Place the JTAG header at board edge with short stubs (<25 mm) to avoid signal-integrity issues at typical 10-30 MHz TCK frequencies. nCONFIG must be tied high through a 10 kΩ resistor; nSTATUS and CONF_DONE are open-drain outputs and require external pull-ups to VCCIO of the relevant bank.
Do NOT confuse the non-G EPM570 with the EPM570G variant when substituting: the G-variant uses 1.8 V VCCINT and a different pinout for the Flash/UFM interface pins. Pin-compatible? Same TQFP-144 footprint, but JTAG/UFM signal locations differ - design re-verification is required. Always double-check the date code suffix: older -5 lots are non-RoHS; new designs should specify C5N (lead-free RoHS).
The TQFP-144 package has a θJA of approximately 35 °C/W (still air) per Altera's packaging thermal model. For typical commercial CPLD designs with modest toggle activity (50-100 MHz, <50% utilisation), the junction temperature rise is well below 20 °C above ambient. Forced-air cooling or reduced I/O toggle duty is only required if ambient exceeds 70 °C or all 116 I/Os toggle simultaneously at fCNT max.
Compliance Information
The bare 'EPM570T144-5' suffix is the original non-RoHS Altera part; for RoHS compliance choose the C5N/C4N re-issues (marked 'C' = commercial RoHS, 'N' = lead-free). The A5N variant is AEC-Q100 automotive qualified.
