EPM570ZM256C7N - 570 LE MAX II Z CPLD, 256-ball MBGA | Altera
MPN: EPM570ZM256C7N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EPM570ZM256C7N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM570ZM256C7N Maximum Ratings & Electrical Characteristics
| Series | MAX II Z |
| Family | MAX II |
| Logic Elements (LE) | 570 |
| Macro Cells | 440 |
| User I/Os | 76 |
| User Flash Memory | 8 Kbits |
| Maximum Operating Frequency | 123.5 MHz |
| Pin-to-Pin Delay (tPD) | 5.0 ns |
| Core Supply Voltage | 1.71 V to 1.89 V (3.3 V with on-chip regulator) |
| I/O Supply Voltages | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Process Technology | 0.18 µm CMOS |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Package | 256-ball MBGA (Micro FBGA), 0.5 mm pitch, 6 × 6 mm |
| Configuration Method | On-chip non-volatile (instant-on, ISP via JTAG) |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP |
| Lead-Free / RoHS | Lead-free / RoHS compliant |
| Logic Family | CMOS |
EPM570ZM256C7N Pin Configuration
| Pin A1 | I/O — User I/O (bank 1) |
| Pin A2 | I/O — User I/O (bank 1) |
| Pin A3 | I/O — User I/O (bank 1) |
| Pin A4 | I/O — User I/O (bank 1) |
| Pin A5 | GND — Ground |
| Pin A6 | I/O — User I/O (bank 2) |
| Pin A7 | I/O — User I/O (bank 2) |
| Pin A8 | I/O — User I/O (bank 2) |
| Pin B1 | I/O — User I/O (bank 1) |
| Pin B2 | I/O — User I/O (bank 1) |
| Pin B3 | VCCIO1 — I/O bank 1 supply voltage |
| Pin B4 | I/O — User I/O (bank 1) |
| Pin B5 | GND — Ground |
| Pin B6 | I/O — User I/O (bank 2) |
| Pin B7 | VCCIO2 — I/O bank 2 supply voltage |
| Pin B8 | I/O — User I/O (bank 2) |
| Pin C1 | I/O — User I/O (bank 1) |
| Pin C2 | I/O — User I/O (bank 1) |
| Pin C3 | I/O — User I/O (bank 1) |
| Pin C4 | VCCINT — Core supply (1.8 V, or via internal regulator from 3.3 V) |
| Pin C5 | TDI — JTAG Test Data In |
| Pin C6 | I/O — User I/O (bank 2) |
| Pin C7 | I/O — User I/O (bank 2) |
| Pin C8 | I/O — User I/O (bank 2) |
| Pin D1 | I/O — User I/O (bank 1) |
| Pin D2 | VCCIO1 — I/O bank 1 supply voltage |
| Pin D3 | I/O — User I/O (bank 1) |
| Pin D4 | TMS — JTAG Test Mode Select |
| Pin D5 | TCK — JTAG Test Clock |
| Pin D6 | TDO — JTAG Test Data Out |
| Pin D7 | I/O — User I/O (bank 2) |
| Pin D8 | VCCIO2 — I/O bank 2 supply voltage |
| Pin E1 | I/O — User I/O (bank 3) |
| Pin E2 | I/O — User I/O (bank 3) |
| Pin E3 | I/O — User I/O (bank 3) |
| Pin E4 | GND — Ground |
| Pin E5 | I/O — User I/O (bank 4) |
| Pin E6 | I/O — User I/O (bank 4) |
| Pin E7 | I/O — User I/O (bank 4) |
| Pin E8 | I/O — User I/O (bank 4) |
| Pin F1 | I/O — User I/O (bank 3) |
| Pin F2 | VCCIO3 — I/O bank 3 supply voltage |
| Pin F3 | I/O — User I/O (bank 3) |
| Pin F4 | GND — Ground |
| Pin F5 | GND — Ground |
| Pin F6 | I/O — User I/O (bank 4) |
| Pin F7 | VCCIO4 — I/O bank 4 supply voltage |
| Pin F8 | I/O — User I/O (bank 4) |
| Pin G1 | I/O — User I/O (bank 3) |
| Pin G2 | I/O — User I/O (bank 3) |
| Pin G3 | I/O — User I/O (bank 3) |
| Pin G4 | I/O — User I/O (bank 3) |
| Pin G5 | I/O — User I/O (bank 4) |
| Pin G6 | I/O — User I/O (bank 4) |
| Pin G7 | I/O — User I/O (bank 4) |
| Pin G8 | I/O — User I/O (bank 4) |
| Pin H1 | GND — Ground |
| Pin H2 | I/O — User I/O (bank 3) |
| Pin H3 | VCCIO3 — I/O bank 3 supply voltage |
| Pin H4 | I/O — User I/O (bank 3) |
| Pin H5 | I/O — User I/O (bank 4) |
| Pin H6 | VCCIO4 — I/O bank 4 supply voltage |
| Pin H7 | I/O — User I/O (bank 4) |
| Pin H8 | GND — Ground |
| Pin J1 | I/O — User I/O (bank 5) |
| Pin J2 | I/O — User I/O (bank 5) |
| Pin J3 | I/O — User I/O (bank 5) |
| Pin J4 | I/O — User I/O (bank 5) |
| Pin J5 | I/O — User I/O (bank 6) |
| Pin J6 | I/O — User I/O (bank 6) |
| Pin J7 | I/O — User I/O (bank 6) |
| Pin J8 | I/O — User I/O (bank 6) |
| Pin K1 | I/O — User I/O (bank 5) |
| Pin K2 | VCCIO5 — I/O bank 5 supply voltage |
| Pin K3 | I/O — User I/O (bank 5) |
| Pin K4 | GND — Ground |
| Pin K5 | GND — Ground |
| Pin K6 | I/O — User I/O (bank 6) |
| Pin K7 | VCCIO6 — I/O bank 6 supply voltage |
| Pin K8 | I/O — User I/O (bank 6) |
| Pin L1 | I/O — User I/O (bank 5) |
| Pin L2 | I/O — User I/O (bank 5) |
| Pin L3 | I/O — User I/O (bank 5) |
| Pin L4 | GND — Ground |
| Pin L5 | I/O — User I/O (bank 6) |
| Pin L6 | I/O — User I/O (bank 6) |
| Pin L7 | I/O — User I/O (bank 6) |
| Pin L8 | I/O — User I/O (bank 6) |
| Pin M1 | I/O — User I/O (bank 5) |
| Pin M2 | VCCIO5 — I/O bank 5 supply voltage |
| Pin M3 | I/O — User I/O (bank 5) |
| Pin M4 | nSTATUS — Configuration status (pull-up required) |
| Pin M5 | nCONFIG — Configuration start input (pull-up required) |
| Pin M6 | I/O — User I/O (bank 6) |
| Pin M7 | VCCIO6 — I/O bank 6 supply voltage |
| Pin M8 | I/O — User I/O (bank 6) |
| Pin N1 | I/O — User I/O (bank 7) |
| Pin N2 | I/O — User I/O (bank 7) |
| Pin N3 | I/O — User I/O (bank 7) |
| Pin N4 | VCCINT — Core supply (1.8 V, or via internal regulator from 3.3 V) |
| Pin N5 | GND — Ground |
| Pin N6 | I/O — User I/O (bank 8) |
| Pin N7 | I/O — User I/O (bank 8) |
| Pin N8 | I/O — User I/O (bank 8) |
| Pin P1 | I/O — User I/O (bank 7) |
| Pin P2 | VCCIO7 — I/O bank 7 supply voltage |
| Pin P3 | I/O — User I/O (bank 7) |
| Pin P4 | I/O — User I/O (bank 7) |
| Pin P5 | GND — Ground |
| Pin P6 | I/O — User I/O (bank 8) |
| Pin P7 | VCCIO8 — I/O bank 8 supply voltage |
| Pin P8 | I/O — User I/O (bank 8) |
| Pin R1 | I/O — User I/O (bank 7) |
| Pin R2 | I/O — User I/O (bank 7) |
| Pin R3 | I/O — User I/O (bank 7) |
| Pin R4 | I/O — User I/O (bank 7) |
| Pin R5 | I/O — User I/O (bank 8) |
| Pin R6 | I/O — User I/O (bank 8) |
| Pin R7 | I/O — User I/O (bank 8) |
| Pin R8 | I/O — User I/O (bank 8) |
| Pin T1 | GND — Ground |
| Pin T2 | I/O — User I/O (bank 7) |
| Pin T3 | VCCIO7 — I/O bank 7 supply voltage |
| Pin T4 | I/O — User I/O (bank 7) |
| Pin T5 | I/O — User I/O (bank 8) |
| Pin T6 | VCCIO8 — I/O bank 8 supply voltage |
| Pin T7 | I/O — User I/O (bank 8) |
| Pin T8 | GND — Ground |
| Pin U1 | I/O — User I/O (bank 7) |
| Pin U2 | I/O — User I/O (bank 7) |
| Pin U3 | I/O — User I/O (bank 7) |
| Pin U4 | GND — Ground |
| Pin U5 | I/O — User I/O (bank 8) |
| Pin U6 | I/O — User I/O (bank 8) |
| Pin U7 | I/O — User I/O (bank 8) |
| Pin U8 | I/O — User I/O (bank 8) |
| Pin V1 | I/O — User I/O (bank 7) |
| Pin V2 | I/O — User I/O (bank 7) |
| Pin V3 | I/O — User I/O (bank 7) |
| Pin V4 | I/O — User I/O (bank 7) |
| Pin V5 | I/O — User I/O (bank 8) |
| Pin V6 | I/O — User I/O (bank 8) |
| Pin V7 | I/O — User I/O (bank 8) |
| Pin V8 | I/O — User I/O (bank 8) |
| Pin W1 | GND — Ground |
| Pin W2 | I/O — User I/O (bank 7) |
| Pin W3 | I/O — User I/O (bank 7) |
| Pin W4 | I/O — User I/O (bank 7) |
| Pin W5 | I/O — User I/O (bank 8) |
| Pin W6 | I/O — User I/O (bank 8) |
| Pin W7 | I/O — User I/O (bank 8) |
| Pin W8 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570ZM256C7N is suitable for 7 applications: Microcontroller I/O Expansion and Bus Muxing, Power-Up Sequencing and Reset Distribution, ASIC/ASSP Replacement and Legacy Interface Bridging, Address Decoding and Chip-Select Generation, Industrial Control and Factory Automation, Portable and Battery-Powered Devices, Telecom and Networking Glue Logic.
Microcontroller I/O Expansion and Bus Muxing
The EPM570ZM256C7N's 76 user I/Os and 570 LEs make it a natural choice for expanding the I/O count or bus width of a host microcontroller that has run out of pins. Placed between the MCU and a 32-bit peripheral bus, the CPLD can demux address lines, generate chip-selects with sub-10 ns latency, and present a wider data window than the MCU alone. The 5.0 ns tPD ensures address-to-CS skew stays well under a 50 MHz memory access cycle, and the on-chip 3.3 V regulator lets the CPLD share the MCU's 3.3 V rail without an extra LDO. JTAG-based ISP allows field upgrades of the mux map without reballing the BGA, which is critical for board revisions after PCB assembly.
Recommended
Power-Up Sequencing and Reset Distribution
The deterministic 5.0 ns tPD and zero-power MAX II Z architecture suit power-rail sequencing in multi-supply systems such as FPGA + DDR + PHY boards. The CPLD can be powered from the always-on 3.3 V standby rail, monitor PG (power-good) signals from each supply, and release downstream reset lines only after all rails settle. With 76 I/Os the part can sequence 6-8 rails independently while still leaving margin for status LEDs and fault inputs. Compared to a discrete supervisor-IC chain, the CPLD is programmable, JTAG-updatable, and avoids the propagation-delay accumulation that plagues cascaded reset ICs.
Recommended
ASIC/ASSP Replacement and Legacy Interface Bridging
Many EOL ASSPs in industrial control boards can be emulated by a MAX II Z CPLD programmed as a state machine plus glue logic. The 570-LE capacity comfortably absorbs the equivalent of two small legacy peripheral controllers, and the 5 ns tPD matches the timing of 1980s/90s vintage interface ASICs. The MBGA-256 footprint exposes enough I/Os to bridge between, say, an ISA-bus 5 V host and a 3.3 V ARM peripheral without external buffers. Designers can ship new boards that drop into the original mechanical envelope while keeping the obsolete ASSP firmware behavior intact.
Recommended
Address Decoding and Chip-Select Generation
In a 32-bit embedded system, the host processor emits a full address bus and needs a unique chip-select for each peripheral region. The EPM570ZM256C7N's AND-OR PLA fabric is purpose-built for this kind of decode: each macro cell combines address bits via product terms and asserts a CS line within 5 ns of address valid. Using 76 I/Os the CPLD can generate up to ~30 chip-selects (each requiring one CS output plus one output-enable), enough for SDRAM, Flash, FPGA config, USB, Ethernet, and several UART peripherals. MultiVolt I/O lets the same CPLD decode both 3.3 V and 5 V address buses simultaneously.
Recommended
Industrial Control and Factory Automation
Factory PLC and motor-control boards demand deterministic logic, long-term supply assurance, and industrial temperature tolerance. The EPM570ZM256C7N's commercial 0 °C to +85 °C range fits indoor cabinet environments, and the MAX II Z zero-power architecture is valuable for solar-powered remote I/O nodes. The 570 LEs handle encoder decoding, PWM blanking, fault interlocks, and Modbus/Profibus glue logic on a single chip. Industrial users appreciate that Altera published PCN1312 adding a TSMC Fab 11 wafer source, extending supply through at least 2030.
Recommended
Portable and Battery-Powered Devices
The MAX II Z variant of the EPM570ZM256C7N is specifically designed for portable applications where quiescent current matters. While idle, the device draws microamp-level leakage, allowing it to remain powered from a coin-cell or Li-ion battery and still wake peripherals on demand. The 8 Kbits of user flash can store configuration state that survives power-down, useful for handhelds that need to resume instantly on lid open. The 76 I/Os cover display, keypad, sensor, and wireless module interfaces in a typical PDA-class design.
Recommended
Telecom and Networking Glue Logic
In router and switch line-card designs, the EPM570ZM256C7N is used for PHY interface bridging, LED driving, and front-panel management. With MultiVolt I/O supporting 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5.0 V, a single CPLD can interface a 1.8 V FPGA to 3.3 V PHYs and 5 V legacy management ICs without level shifters. The 123.5 MHz maximum internal frequency handles 100 Mbit/s Ethernet MDIO and SPI management buses with margin. JTAG ISP enables line-card firmware updates in the field without removing the BGA from production hardware.
Recommended
Recommended Products Summary
Engineering reference data for EPM570ZM256C7N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570ZM256C6N | EPM570ZF256C7N | EPM570M256C5N | EPM570GM256C5N | EPM570F256C5N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | MBGA-256 (256-ball Micro BGA) | MBGA-256 - same | MBGA-256 - same | MBGA-256 - same | MBGA-256 - same | MBGA-256 - same |
| Family / Variant | MAX II Z (zero-power) | MAX II Z (zero-power) | MAX II non-Z | MAX II non-Z | MAX II G | MAX II non-Z |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Speed Grade | -7 | -6 (slower) | -7 (same) | -5 (faster) | -5 (faster) | -5 (faster) |
| Pin-to-Pin Delay (tPD) | 5.0 ns | ~5.5 ns | 5.0 ns | 4.5 ns | 4.5 ns | 4.5 ns |
| User I/Os | 76 | 76 | 76 | 76 | 76 | 76 |
| Core Voltage | 1.8 V (3.3 V via internal regulator) | 1.8 V (3.3 V via internal regulator) | 1.8 V (3.3 V via internal regulator) | 1.8 V (3.3 V via internal regulator) | 1.8 V (3.3 V via internal regulator) | 1.8 V (3.3 V via internal regulator) |
| Quiescent Power Architecture | Zero-power (Z variant) | Zero-power (Z variant) | Standard (non-Z) | Standard (non-Z) | Standard (non-G less efficient) | Standard (non-Z) |
| Operating Temperature | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Approx. Price @ qty-1 (USD) | 18.50 | 16.80 | 17.20 | 19.10 | 20.40 | 17.95 |
Key Differentiators
- Zero-power architecture for battery-powered portable designs (vs EPM570M256C5N)
- Same MBGA-256 footprint as all MAX II EPM570Z/EPM570F/EPM570GF/EPM570M/EPM570GM 256-pin variants (vs EPM570ZM100C7N (MBGA-100))
- Speed grade -7 with 5.0 ns tPD and 123.5 MHz fMAX (vs EPM570ZM256C6N)
- MultiVolt I/O supports 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed-voltage interfacing (vs EPM570T100C5N (TQFP-100))
Design Notes
The MBGA-256 with 0.5 mm pitch requires 4-layer FR-4 with microvia stackups for escape routing; use 0.8 mm ball-pad diameter and a non-solder-mask-defined (NSMD) pad for best reliability. Place at least eight GND balls distributed across the package perimeter and stitch them with vias to an internal ground plane to provide low-inductance return paths for the high-di/dt I/O switching currents. Decouple each VCCIO bank with a 0.1 µF X7R 0402 ceramic placed within 50 mils of the ball, plus one bulk 4.7 µF tantalum per bank.
The MAX II Z on-chip regulator lets you feed the core from a single 3.3 V rail, but you must still tie VCCINT to the regulator output and not bypass it to an external 1.8 V supply unless the design calls for the multi-rail mode. Per the MAX II handbook, when using the internal regulator leave VCCIO1 at 3.3 V and the regulator generates 1.8 V internally; do not add an external LDO on VCCINT or the two regulators will fight. Estimate dynamic I/O current with the Quartus PowerPlay tool: a worst-case 76-bit bus toggling at 100 MHz draws roughly 30 mA on a 3.3 V VCCIO.
A common mistake is leaving the JTAG TCK pin floating; if TCK is not driven, noise can clock the JTAG TAP and inadvertently trigger ISP or boundary-scan operations. Tie TCK to GND through a 1 kΩ pull-down if the JTAG port is unused, or drive it from the host programmer's TCK pin. Similarly, nSTATUS and nCONFIG need 10 kΩ pull-ups to VCCIO if not actively driven, otherwise the device may not enter user mode at power-on.
Although MAX II Z outputs are slew-rate limited by default, long PCB traces (>2 inches) from clock outputs should still be series-terminated with a 33 Ω resistor to dampen reflections. The MultiVolt I/O receivers tolerate 5 V inputs even when VCCIO is 3.3 V, but the absolute-maximum ratings forbid driving the I/O above 4.6 V when VCCIO is below 3.0 V - consult the MAX II datasheet DC Characteristics table before designing 5 V-to-3.3 V bridges.
Place a 4.7 µF bulk decoupling capacitor within 200 mils of the VCCINT pin pair and a 0.1 µF high-frequency bypass within 50 mils. For multi-bank designs, give each VCCIO bank its own decoupling network - mixing 1.8 V and 3.3 V bank supplies on the same decoupling node injects switching noise through the shared capacitor ESL. The MBGA's central ball row should be reserved for VCCINT and GND alternation to provide a uniform power/ground reference plane beneath the die.
Compliance Information
Lead-free per Altera/Intel MAX II device handbook. RoHS and REACH compliance confirmed on distributor listings. AEC-Q100 qualification not applicable for commercial-grade CPLD; industrial-temperature variants exist (EPM570ZM256I7N) but AEC-Q100 is not certified. Conflict-minerals compliance per Altera/Intel CMRT filings.
