EPM9560RC240-20N - MAX 9000 CPLD 560 Macro 240-RQFP | Altera
MPN: EPM9560RC240-20N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for EPM9560RC240-20N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC240-15
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$174.72 / Unit
View Datasheet →EPM9560RC240-10
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View Datasheet →EPM9560RC240-20C
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View Datasheet →EPM9560RC240-20
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$122 / Unit
View Datasheet →EPM9560RC240-15N
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$27.85 / Unit
View Datasheet →EPM9560RC240-15C
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View Datasheet →EPM9560RC240-20N Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 (EPM9560) |
| Logic Type | Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 35 |
| Maximum User I/O Pins | 216 |
| Pin-to-Pin Propagation Delay (tPD1) | 20 ns |
| Internal Counter Frequency (fCNT) | 144 MHz |
| Flip-Flop Setup Time (tSU) | 3.0 ns |
| Supply Voltage | 5.0 V |
| Configuration Technology | EEPROM (in-system programmable) |
| Package | 240-pin RQFP (PowerQuad Flat Pack) |
| Operating Temperature | 0 C to +70 C (commercial) |
| Mounting Type | Surface Mount |
| Speed Grade | -20 (20 ns) |
EPM9560RC240-20N 240-pin rqfp (powerquad flat pack) Pin Configuration Guide
Complete pinout information for EPM9560RC240-20N (240-pin rqfp (powerquad flat pack) package) with 216 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC240-20N.
Refer to the datasheet for full pin configuration.
Estimated pin count: 216 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC240-20N is suitable for 6 applications: Legacy Bus Bridging and Protocol Conversion, Address Decoding and Chip-Select Logic, State Machine and Sequencer Implementation, Glue Logic Consolidation, Industrial Control and Automation, Test and Measurement Instrumentation.
Legacy Bus Bridging and Protocol Conversion
The EPM9560RC240-20N fits legacy bus bridging because its 216 user I/O pins and 560 macrocells can implement wide address/data bus translation between 5.0 V ISA, VME, or custom backplane interfaces and peripheral devices. With a 20 ns pin-to-pin delay and 144 MHz counter frequency, it handles bus-cycle timing with margin at 5.0 V logic levels. The device is placed between two bus domains, decoding addresses in combinatorial macrocells and latching data in registered macrocells. Unlike a modern 3.3 V CPLD, it natively drives 5.0 V TTL/CMOS buses without level shifters, but it consumes more static power and is obsolete, so it suits maintenance of existing boards rather than new designs.
Recommended
Address Decoding and Chip-Select Logic
The EPM9560RC240-20N is well suited to address decoding because its 35 logic array blocks and 560 macrocells can generate dozens of chip-select and enable terms from a wide address bus. The 20 ns tPD1 and 3.0 ns flip-flop setup time allow registered decode outputs that meet typical 5.0 V microprocessor bus timing. In a typical implementation, address lines feed combinatorial macrocells that AND/OR decode terms, while registered macrocells synchronize chip-select assertion to the bus clock. The continuous interconnect array gives deterministic, routing-independent delay, simplifying worst-case timing analysis. The trade-off versus a modern CPLD is higher 5.0 V power and an obsolete supply chain, so the part is best reserved for legacy system repair.
Recommended
State Machine and Sequencer Implementation
The EPM9560RC240-20N implements finite state machines and power-up sequencers using its 560 macrocells, each with a programmable flip-flop featuring individual clock, clear, and preset control. The 144 MHz internal counter frequency supports fast state transitions, while the 3.0 ns flip-flop setup time allows reliable clocking at system speeds. Designers map state registers into macrocells and next-state logic into the logic array, using the continuous interconnect for uniform timing. A key advantage over discrete 74-series logic is single-device integration and in-system reprogrammability via the EEPROM configuration. The limitation is the 5.0 V core and obsolete status, so new sequencer designs should use an active CPLD family instead.
Recommended
Glue Logic Consolidation
The EPM9560RC240-20N consolidates dozens of discrete 74-series glue-logic devices into one 240-pin RQFP CPLD, reducing board area and part count. Its 12,000 usable gates and 560 macrocells absorb counters, shift registers, multiplexers, and random logic, while 216 user I/O pins connect to surrounding circuitry. The EEPROM configuration is instant-on, so no configuration PROM or boot delay is needed, unlike SRAM-based FPGAs. In practice, engineers replace a cluster of 74HC/74LS parts with a single EPM9560 and reprogram it in-system for design revisions. The trade-off is a higher unit cost and obsolete lifecycle versus discrete logic, so the approach suits legacy boards where space and rework reduction matter most.
Recommended
Industrial Control and Automation
The EPM9560RC240-20N suits industrial control because its 5.0 V logic levels interface directly with legacy PLC backplanes, relay drivers, and opto-isolated I/O, and its 216 user I/O pins handle wide parallel control buses. The 560 macrocells implement ladder-logic equivalents, timers, and interlocks, while the 20 ns tPD1 ensures deterministic response to sensor inputs. The device is typically placed on a control card between the host processor and field I/O, decoding commands and latching outputs. The continuous interconnect array provides predictable timing for safety-relevant interlocks. However, the commercial 0 C to +70 C rating limits use to controlled environments, and the obsolete status makes it a maintenance-only choice for industrial retrofits.
Recommended
Test and Measurement Instrumentation
The EPM9560RC240-20N is used in test and measurement equipment for pattern generation, trigger logic, and instrument bus interfacing. Its 144 MHz counter frequency supports fast event counting, and the 560 macrocells implement trigger state machines and timestamp logic. The 216 user I/O pins connect to front-end comparators, DACs, and host interfaces, while the 5.0 V levels match legacy instrument backplanes. In a typical design, the CPLD generates stimulus patterns and captures response data under host control, using registered macrocells for glitch-free outputs. The deterministic interconnect delay aids repeatable measurement timing. The main drawbacks are the obsolete supply chain and higher power versus modern CPLDs, so it is best for servicing existing instruments rather than new product development.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-20N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-15 | EPM9560RC240-10 | EPM9560RC240-20C | EPM9560RC240-20 |
|---|---|---|---|---|---|
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Pin-to-Pin Propagation Delay (tPD1) | 20 ns | 15 ns | 10 ns | 20 ns | 20 ns |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Maximum User I/O Pins | 216 | 216 | 216 | 216 | 216 |
| Internal Counter Frequency (fCNT) | 144 MHz | [DATA_NEEDED] | [DATA_NEEDED] | 144 MHz | 144 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Termination Finish | Lead-free (N suffix) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | Leaded |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lead-free (N suffix) construction (vs EPM9560RC240-20)
- Faster speed grades available in the same footprint (vs EPM9560RC240-15)
- Highest density in the MAX 9000 family (vs EPM9480RC240-20)
Design Notes
The EPM9560RC240-20N requires a regulated 5.0 V supply for both core and I/O. Decouple every VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10 uF capacitor per device. Estimated: at a typical 5.0 V CPLD operating current of a few hundred milliamps, a 0.5 V supply droop would exceed the device tolerance, so keep the 5.0 V rail within +/-5% and verify the regulator can supply the transient current during EEPROM programming.
Route the 240-pin RQFP on a board with at least four layers: a dedicated ground plane directly under the device and a power plane for the 5.0 V rail. Keep high-speed clock traces short and reference them to the ground plane to control impedance. Because the MAX 9000 uses a continuous interconnect array with deterministic delay, timing is dominated by I/O trace length rather than internal routing, so match trace lengths on parallel buses to within a few millimeters.
Do not assume the -20N is interchangeable with non-EPM9560 MAX 9000 devices: the EPM9320, EPM9400, and EPM9480 have fewer macrocells and different pinouts despite sharing the family. Also confirm the N suffix for lead-free assembly; the leaded EPM9560RC240-20 requires a different reflow profile. Finally, because the family is obsolete, program and verify a golden sample before committing production stock.
Compliance Information
The N suffix indicates lead-free (RoHS-compatible) terminations, but no explicit RoHS/REACH declaration was present in the verified web data. AEC-Q100 is not applicable (commercial-grade CPLD).
