EPM9560RC240-20C - MAX 9000 CPLD 560 Macro 240-RQFP | Altera
MPN: EPM9560RC240-20C ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for EPM9560RC240-20C — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560RC240-20
✅ Drop-In✓ In Stock
$122 / Unit
View Datasheet →EPM9560RC240-15
✅ Drop-In✓ In Stock
$174.72 / Unit
View Datasheet →EPM9560RC240-10
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Contact for price
View Datasheet →EPM9480RC240-20
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →EPM9560ARC240-10
✅ Drop-In✓ In Stock
$28.8 / Unit
View Datasheet →EPM9560RC240-20C Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 35 |
| Maximum User I/O Pins | 216 |
| Pin-to-Pin Propagation Delay (tPD1) | 20 ns |
| Internal Counter Frequency (fCNT) | 144 MHz |
| Supply Voltage | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (5.0 V ISP) |
| Package | 240-pin RQFP (PowerQuad/RC) |
| Operating Temperature | 0 C to 70 C (commercial) |
| Mounting Type | Surface Mount |
| Logic Family | CMOS |
| Speed Grade | -20 (20 ns) |
EPM9560RC240-20C 240-pin rqfp (powerquad/rc) Pin Configuration Guide
Complete pinout information for EPM9560RC240-20C (240-pin rqfp (powerquad/rc) package) with 216 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC240-20C.
Refer to the datasheet for full pin configuration.
Estimated pin count: 216 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC240-20C is suitable for 6 applications: PCI/ISA Bus Bridge Logic, Industrial Control State Machines, Telecommunications Line-Card Logic, Legacy System Replacement and Obsolescence Mitigation, Test and Measurement Instrument Control, Military and Aerospace Legacy Upgrades.
PCI/ISA Bus Bridge Logic
The EPM9560RC240-20C fits PCI and ISA bus-bridge glue logic because its 216 user I/O pins and 560 macrocells can absorb address decoding, wait-state generation, and bus arbitration in a single non-volatile device. With a 20 ns pin-to-pin delay and 144 MHz internal counter frequency, it meets the timing budget of 33 MHz PCI and 8 MHz ISA buses with margin. Because the MAX 9000 architecture is EEPROM-based, the bridge logic is live microseconds after power-up, eliminating the boot-PROM delay of SRAM FPGAs. The trade-off is that the 5.0 V supply and non-3.3 V-tolerant I/O require level shifting when bridging to modern low-voltage buses.
Recommended
Industrial Control State Machines
The EPM9560RC240-20C is well suited to industrial control state machines because its 560 macrocells and 35 LABs implement large deterministic FSMs with guaranteed 20 ns worst-case delay, unlike SRAM FPGAs whose routing delay varies with placement. The 5.0 V CMOS I/O interfaces directly with legacy 5 V sensors, relays, and PLC backplanes, and the EEPROM configuration survives power cycling without a configuration PROM. At 144 MHz fCNT the device can oversample slow industrial signals for debouncing and edge detection. Designers should note the 0 C to 70 C commercial rating and select an industrial-temperature MAX 9000 variant if the enclosure exceeds 70 C.
Recommended
Telecommunications Line-Card Logic
The EPM9560RC240-20C serves telecommunications line-card glue logic where 216 I/O pins map multiple T1/E1 framers, HDLC controllers, and backplane interfaces into one CPLD. Its 560 macrocells implement channel-associated signaling state machines and timeslot interchange control, while the 20 ns tPD1 keeps setup/hold margins comfortable at 8 MHz backplane rates. The non-volatile EEPROM configuration means line cards resume traffic immediately after a power hit, an important availability requirement in central-office equipment. The 5.0 V core simplifies interfacing to legacy telecom components, but modern 3.3 V line-card controllers need level translation on shared buses.
Recommended
Legacy System Replacement and Obsolescence Mitigation
The EPM9560RC240-20C is frequently used to replace obsolete PALs, GALs, and discrete 74-series glue logic in legacy systems because one 240-pin RQFP device absorbs dozens of small logic packages while preserving 5.0 V TTL-compatible levels. Its 12,000 usable gates and 560 macrocells consolidate address decoders, wait-state generators, and DMA controllers into a single reprogrammable part, reducing board area and component count. Because the MAX 9000 family is itself now obsolete, designers should stock drop-in same-family parts such as the EPM9560RC240-20 and EPM9560RC240-15, or plan a migration to a modern CPLD with a level-shifting interface.
Recommended
Test and Measurement Instrument Control
The EPM9560RC240-20C is used in test and measurement instruments for trigger logic, counter/timer control, and front-panel interface sequencing. Its 144 MHz internal counter frequency supports precision event counting, while the 20 ns deterministic delay ensures repeatable trigger latency - a requirement in automated test equipment where jitter degrades measurement uncertainty. The 216 user I/O pins drive front-panel LEDs, relays, and attenuator control lines directly from 5.0 V CMOS outputs. The EEPROM configuration guarantees the instrument boots into a known logic state without a configuration PROM, simplifying field service and calibration.
Recommended
Military and Aerospace Legacy Upgrades
The EPM9560RC240-20C appears in military and aerospace legacy upgrades where 5.0 V logic and instant-on EEPROM configuration are mandatory. Its 560 macrocells implement redundant voting logic, bus monitors, and interface protocol converters, and the deterministic 20 ns timing simplifies worst-case timing analysis required by safety reviews. The non-volatile configuration eliminates single-event-upset risk in the configuration memory that affects SRAM FPGAs, an advantage in radiation-adjacent environments. Note that the commercial 0 C to 70 C grade is not suitable for extended-temperature military use; industrial or military-temperature MAX 9000 variants should be selected for those programs.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-20C — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-20 | EPM9560RC240-15 | EPM9480RC240-20 | EPM9560ARC240-10 |
|---|---|---|---|---|---|
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 480 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 10,000 | 12,000 |
| Pin-to-Pin Delay (tPD1) | 20 ns | 20 ns | 15 ns | 20 ns | 10 ns |
| Internal Counter Frequency (fCNT) | 144 MHz | 144 MHz | 144 MHz | 144 MHz | 144 MHz |
| Maximum User I/O Pins | 216 | 216 | 216 | 216 | 216 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Operating Temperature | 0 C to 70 C | 0 C to 70 C | 0 C to 70 C | 0 C to 70 C | 0 C to 70 C |
Key Differentiators
- Higher logic capacity than EPM9480 in the same footprint (vs EPM9480RC240-20)
- Non-volatile EEPROM configuration with instant-on operation (vs EPM9560ARC240-10)
- Deterministic 20 ns pin-to-pin timing (vs EPM9560RC240-15)
Design Notes
The EPM9560RC240-20C requires a well-regulated 5.0 V supply with adequate decoupling on every VCC pin. Place a 0.1 uF ceramic capacitor within 5 mm of each VCC/GND pin pair and add a 10 uF bulk capacitor per power plane. Estimated: at 144 MHz operation the device can draw several hundred milliamps, so size the regulator and copper pour for the worst-case switching current rather than the quiescent value. Verify the actual ICC from the MAX 9000 datasheet for your design's toggle rate.
At 144 MHz internal counter frequency and 20 ns pin-to-pin delay, the EPM9560RC240-20C's 240-pin RQFP package demands controlled-impedance routing for high-speed I/O. Keep clock traces short, reference them to a solid ground plane, and terminate long nets with series resistors near the driver. Avoid routing high-speed signals across plane splits, which causes return-path discontinuities and radiated emissions. The 5.0 V CMOS output edges are fast enough to require attention to crosstalk between adjacent I/O pins.
The EPM9560RC240-20C is a 5.0 V-only device and is not fully 3.3 V tolerant on all pins. Connecting 3.3 V logic directly to its inputs can forward-bias protection structures and cause excessive current; use level shifters or series resistors and verify input voltage limits in the MAX 9000 datasheet. Also confirm the 0 C to 70 C commercial temperature grade is adequate for the enclosure, and remember the part is obsolete - qualify a drop-in same-family replacement before production.
Compliance Information
No compliance data was present in the verified web data for the EPM9560RC240-20C. The device is an obsolete Altera MAX 9000 CPLD; RoHS, REACH, lead-free, and halogen-free status must be confirmed with the distributor or manufacturer before use in regulated markets.
