EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
N.º da peça: EPM7096QC100-10 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $12.5 | $12,50 |
| 10 | $11.25 | $112,50 |
| 100 | $9.8 | $980,00 |
| 500 | $8.4 | $4.200,00 |
| 1.000 | $7.1 | $7.100,00 |
EPM7096QC100-10 Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the instant-on characteristics of PAL/GAL architectures with higher macrocell density and deterministic timing. Within the broader taxonomy, the CPLD belongs to programmable logic devices, sits alongside FPGAs as the two main branches of digital programmable logic, and ultimately falls under the semiconductor and integrated circuit hierarchy. The MAX 7000 series was Altera's mainstream 5V CPLD family widely adopted for bus interface glue logic, address decoding, state-machine control, and peripheral bridging before 3.3V FPGAs became dominant.
Key specifications include 96 macrocells, 4 Logic Array Blocks, 76 available I/O pins, 10ns tPD (pin-to-pin delay), 100 MHz maximum operating frequency, and 5V VCC. The device supports JTAG boundary-scan test per IEEE 1149.1 and is PCI-compliant in the -10 speed grade. The PQFP-100 (Plastic Quad Flat Pack, 20×14 mm, 0.65mm pitch) gives a robust through-hole-compatible footprint and is one of the most widely supported legacy CPLD packages on long-lifecycle industrial designs.
Typical applications include ISA/PCI bus decoding, peripheral glue logic, address decoding, state-machine control, and reconfigurable I/O expansion in industrial control, telecom, and embedded systems. When designing with this part, note that the MAX 7000 (non-S) variant uses a parallel programming interface; for ISP via JTAG, verify the exact device suffix against the datasheet. The PQFP-100 footprint requires a fine-pitch PCB land pattern; ensure adequate thermal relief for the exposed die pad and follow JEDEC J-STD-020 MSL handling for any programming or rework steps.
Alternativas drop-in para EPM7096QC100-10 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM7096QC100-10 (mesmo formato e footprint) — diferindo em Operating Temperature, Package, Programming Interface, Mounting Type, Supply Voltage (VCC).
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM7096LC84-10
✅ Drop-In✓ Em estoque
$5.1 / unidade
Ver ficha técnica →EPM7096LC84-15
✅ Drop-In✓ Em estoque
$9.85 / unidade
Ver ficha técnica →EPM7096LC84-7
✅ Drop-In✓ Em estoque
$19.85 / unidade
Ver ficha técnica →EPM7096LC68-15
✅ Drop-In✓ Em estoque
$7.2 / unidade
Ver ficha técnica →EPM7096LC68-7
✅ Drop-In✓ Em estoque
$9.95 / unidade
Ver ficha técnica →EPM7096QC100-10 Classificações máximas e características elétricas
| Family | MAX 7000 |
| Macrocells | 96 |
| Logic Array Blocks | 4 |
| User I/O Pins | 76 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Operating Frequency | 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Technology | EEPROM-based CMOS |
| Programming Interface | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) on MAX 7000S |
| PCI Compliance | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) |
| Temperatura de operação | 0 °C to +70 °C (commercial) |
| Encapsulamento | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) |
| Tipo de montagem | Surface Mount |
Configuração de pinos do EPM7096QC100-10
| Pino 1 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 2 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 3 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 4 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 5 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 6 | GND — Ground |
| Pino 7 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 8 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 9 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 10 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 11 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 12 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 13 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 14 | I/O — User I/O pin (Macrocell I/O bank 1) |
| Pino 15 | GND — Ground |
| Pino 16 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 17 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 18 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 19 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 20 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 21 | GND — Ground |
| Pino 22 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 23 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 24 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 25 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 26 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 27 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 28 | GND — Ground |
| Pino 29 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 30 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 31 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 32 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 33 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 34 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 35 | I/O — User I/O pin (Macrocell I/O bank 2) |
| Pino 36 | GND — Ground |
| Pino 37 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 38 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 39 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 40 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 41 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 42 | VCC — +5V supply voltage |
| Pino 43 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 44 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 45 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 46 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 47 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 48 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 49 | GND — Ground |
| Pino 50 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 51 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 52 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 53 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 54 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 55 | I/O — User I/O pin (Macrocell I/O bank 3) |
| Pino 56 | GND — Ground |
| Pino 57 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 58 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 59 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 60 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 61 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 62 | VCC — +5V supply voltage |
| Pino 63 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 64 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 65 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 66 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 67 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 68 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 69 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 70 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 71 | I/O — User I/O pin (Macrocell I/O bank 4) |
| Pino 72 | GND — Ground |
| Pino 73 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 74 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 75 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 76 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 77 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 78 | VCC — +5V supply voltage |
| Pino 79 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 80 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 81 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 82 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 83 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 84 | I/O — User I/O pin (Macrocell I/O bank 5) |
| Pino 85 | GND — Ground |
| Pino 86 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 87 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 88 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 89 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 90 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 91 | VCC — +5V supply voltage |
| Pino 92 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 93 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 94 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 95 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 96 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 97 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 98 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 99 | I/O — User I/O pin (Macrocell I/O bank 6) |
| Pino 100 | I/O — User I/O pin (Macrocell I/O bank 6) |
Aplicações típicas
EPM7096QC100-10 é adequado para 6 aplicaçãos: ISA/PCI Bus Address Decoding, Peripheral Glue Logic Replacement, State-Machine Control, Reconfigurable I/O Expansion, Industrial Control Boards, Telecom Backplane Bridging.
ISA/PCI Bus Address Decoding
The EPM7096QC100-10's 10 ns pin-to-pin propagation delay and PCI compliance at -10 speed grade make it well-suited for ISA/PCI bus address decoding in legacy industrial PCs and add-in cards. With 96 macrocells organized into 4 Logic Array Blocks, the device can hold multiple address-decoder windows, chip-select generators, and wait-state logic in a single non-volatile part. The 76 user I/Os easily accommodate full 32-bit address and 16/32-bit data bus multiplexing, while the 5V VCC integrates directly with PCI 5V signaling without level shifters.
Recomendado
Peripheral Glue Logic Replacement
The EPM7096QC100-10 is widely used to replace multiple 74-series TTL/CMOS glue-logic chips with a single programmable device, reducing board area and BOM cost. Its 4 Logic Array Blocks and 96 macrocells can implement latches, multiplexers, parity generators, and interrupt controllers that previously required 5 to 10 discrete packages. The 10 ns tPD keeps propagation through the CPLD below one PCI clock cycle, ensuring no setup-time violations on peripheral buses.
Recomendado
State-Machine Control
Implementing complex state machines is a classic CPLD use case, and the EPM7096QC100-10's 96 macrocells easily encode FSMs with 16 to 32 states plus output decoding. The deterministic 10 ns tPD enables tight state-transition timing with no jitter from asynchronous routing, while the EEPROM-based non-volatile configuration means the state machine powers up instantly with no external boot PROM. Designers can iterate on the FSM in Altera's legacy MAX+PLUS II toolchain and re-program the device in-circuit via ByteBlaster.
Recomendado
Reconfigurable I/O Expansion
The EPM7096QC100-10's 76 user I/O pins make it ideal for reconfigurable I/O expansion in legacy embedded systems where a microcontroller lacks enough pins. The 5V-tolerant I/Os interface directly to 5V peripherals, while the CPLD can implement I2C, SPI, or parallel-bit-banged protocols in firmware-defined logic. Combined with 96 macrocells, one EPM7096QC100-10 can replace an entire I/O-expander ASIC plus its support glue in industrial control boards.
Recomendado
Industrial Control Boards
Industrial PLCs, motor controllers, and process-control boards have used the EPM7096QC100-10 for over two decades thanks to its 0–70 °C commercial temperature range, robust PQFP-100 footprint, and EEPROM non-volatility. The device hosts encoder interfaces, PWM generators, and fault-logic circuits that benefit from the CPLD's deterministic timing. Long-term field-installed bases in factories continue to require this part for maintenance, even as new designs migrate to MAX II or MAX V.
Recomendado
Telecom Backplane Bridging
The EPM7096QC100-10 serves legacy telecom backplanes where it bridges E1/T1 framers, HDLC controllers, and time-slot interchangers through deterministic glue logic. The 100-pin PQFP gives generous I/O headroom for backplane connectors, while 5V VCC and 10 ns tPD meet the timing margins of older TDM buses. PCI-compliance at -10 speed grade ensures interoperability with industry-standard cPCI bridges used in telecom line cards.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM7096QC100-10 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM7096LC84-10 | EPM7096LC84-15 | EPM7096LC84-7 | EPM7096LC68-15 | EPM7096LC68-7 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 100-pin PQFP | 84-pin PLCC (verify package variant) | 84-pin PLCC (verify package variant) | 84-pin PLCC (verify package variant) | 68-pin PLCC (verify package variant) | 68-pin PLCC (verify package variant) |
| Family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000 |
| Macrocells | 96 | 96 | 96 | 96 | 96 | 96 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 15 ns (+50%) | 7 ns (-30%) | 15 ns (+50%) | 7 ns (-30%) |
| Supply Voltage | 5 V (4.75–5.25 V) | 5 V (4.75–5.25 V) | 5 V (4.75–5.25 V) | 5 V (4.75–5.25 V) | 5 V (4.75–5.25 V) | 5 V (4.75–5.25 V) |
| User I/O Pins | 76 | 68 (PLCC-84) | 68 (PLCC-84) | 68 (PLCC-84) | 52 (PLCC-68) | 52 (PLCC-68) |
| Logic Array Blocks | 4 | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principais diferenciais
- Faster 10 ns tPD speed grade compared to -15 variants (vs EPM7096LC84-15)
- Largest I/O count in the EPM7096 family with 100-pin PQFP (vs EPM7096LC68-15)
- Same MAX 7000 die as the LC family variants — guaranteed architecture compatibility (vs EPM7096LC84-10)
Notas de projeto
The EPM7096QC100-10 requires a stable +5 V supply within 4.75 V to 5.25 V. Place a 0.1 µF ceramic decoupling capacitor as close as possible to each VCC pin (4 pins: 42, 62, 78, 91) and add a 10 µF tantalum bulk capacitor at the board supply input. Multiple GND pins (6, 15, 21, 28, 36, 49, 56, 72, 85) must all be connected to a low-impedance ground plane to prevent ground-bounce-induced logic errors, especially critical at the -10 ns tPD speed grade.
The PQFP-100 package has a 0.65 mm lead pitch and requires a fine-pitch PCB land pattern compliant with IPC-7351. Use NSMD (non-solder mask defined) pads for better solder joint reliability, and follow JEDEC J-STD-020 MSL handling procedures for any rework. The 20×14 mm body has reasonable thermal dissipation for the CMOS core; a continuous ground plane directly under the device acts as a thermal spreader and provides reference for high-speed signals.
Three common pitfalls when designing with the EPM7096QC100-10: (1) confusing the MAX 7000 base variant (this part, parallel programming only) with the MAX 7000S variant (EPM7096S prefix) which adds JTAG ISP — verify the exact MPN suffix before designing the programming interface; (2) exceeding 5.25 V VCC absolute maximum will permanently damage the EEPROM cells; (3) leaving unused I/O pins floating can cause excessive ICC supply current — set unused pins to output-low or input with internal pull-up enabled in the MAX+PLUS II design file.
At 10 ns tPD, the EPM7096QC100-10 drives 5V CMOS signals with rise/fall times around 2–3 ns. Route output traces as 50 Ω microstrip or stripline on the ground-plane-referenced PCB to control reflections on long traces. Place series damping resistors (22–33 Ω) at outputs driving heavily-loaded buses to reduce ground bounce. For clock inputs, keep traces short and well-isolated from switching I/O to maintain timing margins across the 0–70 °C commercial temperature range.
Informações de conformidade
RoHS, REACH, lead-free and halogen-free status are not explicitly stated in the verified web data for this obsolete Altera/Intel MAX 7000 part. EPM7096QC100-10 was originally released before RoHS became mandatory and many MAX 7000 production lots are non-RoHS — request a compliance certificate from the distributor before using in RoHS-restricted designs.
