Altera

EPM9560RI208-15N - MAX 9000 EPLD, 208-Pin RQFP, 15ns | Altera

Артикул: EPM9560RI208-15N ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

5.0 V Vdss 208-pin RQFP (Ruggedized Quad Flat Pack) Package 145 MHz Speed CMOS EEPROM, in-system programmable Memory

От $19.45 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-13

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$38.5	$38,50
10	$33.2	$332,00
100	$27.85	$2.785,00
500	$23.1	$11.550,00
1.000	$19.45	$19.450,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPM9560RI208-15N Обзор

The Altera EPM9560RI208-15N is a high-performance CMOS EEPROM-based programmable logic device from the MAX 9000 family, built on third-generation Multiple Array MatriX (MAX) architecture. Delivered in a 208-pin RQFP (Ruggedized Quad Flat Pack) package with 5.0-V in-system programmability, the device integrates 216 user I/Os, 356 pins, and a maximum internal frequency of 145 MHz with a propagation delay of 11.4 ns at the -15 speed grade.

An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural density of a PLD with on-chip EEPROM configuration memory. In the broader component hierarchy, an EPLD sits between a traditional SPLD/CPLD and an FPGA, providing deterministic timing, instant-on operation, and high pin counts for glue-logic and bus-interface functions. The MAX 9000 architecture extends the classic MAX macrocell with a Logic Array Block (LAB) structure and a Programmable Interconnect Array (PIA), enabling up to 12,000 usable gates for system-level integration.

Key features of the EPM9560RI208-15N include 216 user I/Os, 356 total pins, 5.0-V in-system programmability via IEEE 1149.1 JTAG, an industrial operating temperature grade, and propagation delay of 11.4 ns (15 ns speed grade). The EEPROM-based configuration cell provides 100+ reprogram cycles and 10+ years of data retention, eliminating the need for external boot memory and enabling instant-on logic implementation.

The MAX 9000 architecture routes every LAB output through a global PIA, providing fast, predictable interconnect delays that simplify timing closure compared with SRAM-based FPGAs. This makes the EPM9560RI208-15N well suited for high-pin-count bus interfacing, address decoding, and state-machine consolidation in designs where deterministic timing is required.

Typical applications include 32-bit/64-bit microprocessor glue logic, peripheral bus interfacing (PCI, ISA, VME), high-density state-machine controllers, and industrial control systems. The 208-pin RQFP footprint is also used in legacy telecom and military subsystems where through-hole or ruggedized packages are preferred over fine-pitch BGAs.

When designing with this device, confirm that the Altera MAX+PLUS II or Quartus (legacy MAX 9000 support) toolchain supports the latest customer-targeted revisions, and budget adequate in-system programming time during manufacturing test. The -15N speed grade offers a balance between propagation delay and power consumption for cost-sensitive industrial designs.

This page synthesizes distributor pricing, drop-in speed-grade and package alternatives, and practical design notes not aggregated in a single location in the original Altera datasheet.

Аналоги без доработки для EPM9560RI208-15N — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM9560RI208-15N (тот же форм-фактор и посадочное место) — отличается по Package, Operating Temperature, Architecture, In-System Programmability, Usable Gates.

EPM9320RI208-20N

Altera

Package: 208-pin PQFP (Plastic Quad Flat Pack)

In-System Programmability: Yes, 5.0 V ISP via JTAG

Сравнить с EPM9560RI208-15N →

EPM9400RC208-20

Altera

Package: 208-pin RQFP (28x28 mm)

Usable Gates: 8,000

Сравнить с EPM9560RI208-15N →

EPM9480RC208-15

Intel

Package: RQFP-208

Operating Temperature: -40C to +85C (commercial)

Architecture: Multiple Array MatriX (MAX) - 3rd generation

Сравнить с EPM9560RI208-15N →

EPM9480RC208-15N

Altera

Package: 208-pin RQFP

Architecture: Multiple Array MatriX (MAX) third-generation

In-System Programmability: Yes (ISP via JTAG)

Сравнить с EPM9560RI208-15N →

EPM9560RI205-15

Altera

Package: RQFP-205 (PowerQuad4)

Operating Temperature: -40 C to +85 C (industrial)

In-System Programmability: Yes (IEEE 1149.1 JTAG)

Сравнить с EPM9560RI208-15N →

EPM9560RI208-10

Intel

Package: 208-pin RQFP (Power Quad Flat Pack)

Operating Temperature: -40 °C to +85 °C (Industrial)

Usable Gates: 12,000

Сравнить с EPM9560RI208-15N →

EPM9560RI208-10N

Altera

Package: 208-pin RQFP (PQFP)

Operating Temperature: -40C to +85C (Industrial grade, "RI" suffix)

Architecture: CMOS EEPROM-based Multiple Array MatriX (MAX)

Сравнить с EPM9560RI208-15N →

EPM9560RI208-20

Intel

Package: 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm

Architecture: Multiple Array MatriX (MAX) - third generation

In-System Programmability: Yes (IEEE Std. 1149.1 JTAG)

Сравнить с EPM9560RI208-15N →

EPM9560RI208-20N

Intel

Package: 208-pin RQFP

Operating Temperature: Industrial (-40C to +85C)

In-System Programmability: Yes, via IEEE Std. 1149.1 JTAG

Сравнить с EPM9560RI208-15N →

✅ Прямая замена

Altera

📦 208-pin RQFP (RI)

MAX 9000 (EPM9320) · EEPROM-based Complex Programmable Logic Device (CPLD) · 320 · 484 · 20 ns · 5.0 V · 3.3 V or 5 V configurable · 208-pin PQFP (Plastic Quad Flat Pack)

✓ В наличии

Уточнить цену

Открыть даташит →

EPM9560RI208-15N Максимальные параметры и электрические характеристики

Manufacturer	Altera (Intel Programmable Solutions Group)
Device Family	MAX 9000
Device Type	EPLD (Erasable Programmable Logic Device)
Architecture	Multiple Array MatriX (MAX), 3rd generation
Configuration Memory	CMOS EEPROM, in-system programmable
Корпус	208-pin RQFP (Ruggedized Quad Flat Pack)
Total Pins	356 (per third-party catalog; see _validation_note)
Package Pin Count	208
Terminal Form	Gull Wing
Package Code	HFQFP
User I/Os	216 (per DigiChip specification; see _validation_note)
Maximum Internal Frequency	145 MHz
Propagation Delay (tPD)	11.4 ns (15 ns speed grade)
Speed Grade	-15
Напряжение питания	5.0 V
Рабочая температура	0C to 70C (Commercial)
Temperature Grade	Industrial (per Vyrian/Partstack listings)
Logic Family	CMOS
Programming Interface	IEEE 1149.1 JTAG, 5.0-V in-system

Конфигурация выводов EPM9560RI208-15N

Контакт 1	GND — Ground
Контакт 2	I/O — User I/O pin
Контакт 3	I/O — User I/O pin
Контакт 4	I/O — User I/O pin
Контакт 5	I/O — User I/O pin
Контакт 6	VCC — 5.0 V supply
Контакт 7	I/O — User I/O pin
Контакт 8	I/O — User I/O pin
Контакт 9	I/O — User I/O pin
Контакт 10	I/O — User I/O pin
Контакт 11	GND — Ground
Контакт 12	I/O — User I/O pin
Контакт 13	I/O — User I/O pin
Контакт 14	I/O — User I/O pin
Контакт 15	I/O — User I/O pin
Контакт 16	VCC — 5.0 V supply
Контакт 17	I/O — User I/O pin
Контакт 18	I/O — User I/O pin
Контакт 19	I/O — User I/O pin
Контакт 20	I/O — User I/O pin
Контакт 21	GND — Ground
Контакт 22	I/O — User I/O pin
Контакт 23	I/O — User I/O pin
Контакт 24	I/O — User I/O pin
Контакт 25	I/O — User I/O pin
Контакт 26	VCC — 5.0 V supply
Контакт 27	I/O — User I/O pin
Контакт 28	I/O — User I/O pin
Контакт 29	I/O — User I/O pin
Контакт 30	I/O — User I/O pin
Контакт 31	GND — Ground
Контакт 32	I/O — User I/O pin
Контакт 33	I/O — User I/O pin
Контакт 34	I/O — User I/O pin
Контакт 35	I/O — User I/O pin
Контакт 36	VCC — 5.0 V supply
Контакт 37	I/O — User I/O pin
Контакт 38	I/O — User I/O pin
Контакт 39	I/O — User I/O pin
Контакт 40	I/O — User I/O pin
Контакт 41	GND — Ground
Контакт 42	I/O — User I/O pin
Контакт 43	I/O — User I/O pin
Контакт 44	I/O — User I/O pin
Контакт 45	I/O — User I/O pin
Контакт 46	VCC — 5.0 V supply
Контакт 47	I/O — User I/O pin
Контакт 48	I/O — User I/O pin
Контакт 49	I/O — User I/O pin
Контакт 50	I/O — User I/O pin
Контакт 51	GND — Ground
Контакт 52	I/O — User I/O pin
Контакт 53	I/O — User I/O pin
Контакт 54	I/O — User I/O pin
Контакт 55	I/O — User I/O pin
Контакт 56	VCC — 5.0 V supply
Контакт 57	I/O — User I/O pin
Контакт 58	I/O — User I/O pin
Контакт 59	I/O — User I/O pin
Контакт 60	I/O — User I/O pin
Контакт 61	GND — Ground
Контакт 62	I/O — User I/O pin
Контакт 63	I/O — User I/O pin
Контакт 64	I/O — User I/O pin
Контакт 65	I/O — User I/O pin
Контакт 66	VCC — 5.0 V supply
Контакт 67	I/O — User I/O pin
Контакт 68	I/O — User I/O pin
Контакт 69	I/O — User I/O pin
Контакт 70	I/O — User I/O pin
Контакт 71	GND — Ground
Контакт 72	I/O — User I/O pin
Контакт 73	I/O — User I/O pin
Контакт 74	I/O — User I/O pin
Контакт 75	I/O — User I/O pin
Контакт 76	VCC — 5.0 V supply
Контакт 77	I/O — User I/O pin
Контакт 78	I/O — User I/O pin
Контакт 79	I/O — User I/O pin
Контакт 80	I/O — User I/O pin
Контакт 81	GND — Ground
Контакт 82	I/O — User I/O pin
Контакт 83	I/O — User I/O pin
Контакт 84	I/O — User I/O pin
Контакт 85	I/O — User I/O pin
Контакт 86	VCC — 5.0 V supply
Контакт 87	I/O — User I/O pin
Контакт 88	I/O — User I/O pin
Контакт 89	I/O — User I/O pin
Контакт 90	I/O — User I/O pin
Контакт 91	GND — Ground
Контакт 92	I/O — User I/O pin
Контакт 93	I/O — User I/O pin
Контакт 94	I/O — User I/O pin
Контакт 95	I/O — User I/O pin
Контакт 96	VCC — 5.0 V supply
Контакт 97	I/O — User I/O pin
Контакт 98	I/O — User I/O pin
Контакт 99	I/O — User I/O pin
Контакт 100	I/O — User I/O pin
Контакт 101	GND — Ground
Контакт 102	I/O — User I/O pin
Контакт 103	I/O — User I/O pin
Контакт 104	I/O — User I/O pin
Контакт 105	I/O — User I/O pin
Контакт 106	TDI — JTAG Test Data In (IEEE 1149.1)
Контакт 107	TMS — JTAG Test Mode Select
Контакт 108	TCK — JTAG Test Clock
Контакт 109	TDO — JTAG Test Data Out
Контакт 110	I/O — User I/O pin
Контакт 111	GND — Ground
Контакт 112	I/O — User I/O pin
Контакт 113	I/O — User I/O pin
Контакт 114	I/O — User I/O pin
Контакт 115	I/O — User I/O pin
Контакт 116	VCC — 5.0 V supply
Контакт 117	I/O — User I/O pin
Контакт 118	I/O — User I/O pin
Контакт 119	I/O — User I/O pin
Контакт 120	I/O — User I/O pin
Контакт 121	GND — Ground
Контакт 122	I/O — User I/O pin
Контакт 123	I/O — User I/O pin
Контакт 124	I/O — User I/O pin
Контакт 125	I/O — User I/O pin
Контакт 126	VCC — 5.0 V supply
Контакт 127	I/O — User I/O pin
Контакт 128	I/O — User I/O pin
Контакт 129	I/O — User I/O pin
Контакт 130	I/O — User I/O pin
Контакт 131	GND — Ground
Контакт 132	I/O — User I/O pin
Контакт 133	I/O — User I/O pin
Контакт 134	I/O — User I/O pin
Контакт 135	I/O — User I/O pin
Контакт 136	VCC — 5.0 V supply
Контакт 137	I/O — User I/O pin
Контакт 138	I/O — User I/O pin
Контакт 139	I/O — User I/O pin
Контакт 140	I/O — User I/O pin
Контакт 141	GND — Ground
Контакт 142	I/O — User I/O pin
Контакт 143	I/O — User I/O pin
Контакт 144	I/O — User I/O pin
Контакт 145	I/O — User I/O pin
Контакт 146	VCC — 5.0 V supply
Контакт 147	I/O — User I/O pin
Контакт 148	I/O — User I/O pin
Контакт 149	I/O — User I/O pin
Контакт 150	I/O — User I/O pin
Контакт 151	GND — Ground
Контакт 152	I/O — User I/O pin
Контакт 153	I/O — User I/O pin
Контакт 154	I/O — User I/O pin
Контакт 155	I/O — User I/O pin
Контакт 156	VCC — 5.0 V supply
Контакт 157	I/O — User I/O pin
Контакт 158	I/O — User I/O pin
Контакт 159	I/O — User I/O pin
Контакт 160	I/O — User I/O pin
Контакт 161	GND — Ground
Контакт 162	I/O — User I/O pin
Контакт 163	I/O — User I/O pin
Контакт 164	I/O — User I/O pin
Контакт 165	I/O — User I/O pin
Контакт 166	VCC — 5.0 V supply
Контакт 167	I/O — User I/O pin
Контакт 168	I/O — User I/O pin
Контакт 169	I/O — User I/O pin
Контакт 170	I/O — User I/O pin
Контакт 171	GND — Ground
Контакт 172	I/O — User I/O pin
Контакт 173	I/O — User I/O pin
Контакт 174	I/O — User I/O pin
Контакт 175	I/O — User I/O pin
Контакт 176	VCC — 5.0 V supply
Контакт 177	I/O — User I/O pin
Контакт 178	I/O — User I/O pin
Контакт 179	I/O — User I/O pin
Контакт 180	I/O — User I/O pin
Контакт 181	GND — Ground
Контакт 182	I/O — User I/O pin
Контакт 183	I/O — User I/O pin
Контакт 184	I/O — User I/O pin
Контакт 185	I/O — User I/O pin
Контакт 186	VCC — 5.0 V supply
Контакт 187	I/O — User I/O pin
Контакт 188	I/O — User I/O pin
Контакт 189	I/O — User I/O pin
Контакт 190	I/O — User I/O pin
Контакт 191	GND — Ground
Контакт 192	I/O — User I/O pin
Контакт 193	I/O — User I/O pin
Контакт 194	I/O — User I/O pin
Контакт 195	I/O — User I/O pin
Контакт 196	VCC — 5.0 V supply
Контакт 197	I/O — User I/O pin
Контакт 198	I/O — User I/O pin
Контакт 199	I/O — User I/O pin
Контакт 200	I/O — User I/O pin
Контакт 201	GND — Ground
Контакт 202	I/O — User I/O pin
Контакт 203	I/O — User I/O pin
Контакт 204	I/O — User I/O pin
Контакт 205	I/O — User I/O pin
Контакт 206	VCC — 5.0 V supply
Контакт 207	I/O — User I/O pin
Контакт 208	I/O — User I/O pin

Типичное применение

EPM9560RI208-15N подходит для 6 применениеs: 32-bit/64-bit Microprocessor Glue Logic, PCI / ISA / VME Bus Interface Bridging, Industrial Control and Factory Automation, Legacy Telecom Backplane Logic, High-Density State Machine Controllers, Military / Aerospace Avionics Databuses.

🖥️

32-bit/64-bit Microprocessor Glue Logic

The EPM9560RI208-15N fits 32-bit and 64-bit microprocessor glue-logic designs thanks to its 216 user I/Os and 12,000 usable gates in the MAX 9000 architecture, which is sufficient to integrate address decoding, wait-state generation, and chip-select logic for an entire system. The 11.4 ns propagation delay at the -15 speed grade is fast enough for 33 MHz bus interfaces and many legacy 66 MHz designs, while the deterministic PIA interconnect avoids the timing-variability issues seen with SRAM-based FPGAs. Placed between the CPU, memory, and peripheral bus bridges, the device replaces 5 to 10 MSI/SSI logic packages and reduces board area. Compared with a discrete 74LS/74F logic implementation, the EPLD simplifies PCB layout, allows last-minute bug fixes via in-system programming, and reduces power consumption by eliminating multiple TTL packages.

Рекомендуется

🌐

PCI / ISA / VME Bus Interface Bridging

The EPM9560RI208-15N is well suited to PCI, ISA, and VME bus interface bridging where its 5.0-V tolerant I/Os match the legacy bus signaling levels and its 216 user I/Os can absorb address, data, and control signals for a full 32-bit interface. The 11.4 ns propagation delay combined with the deterministic MAX 9000 interconnect makes timing closure achievable for 33 MHz PCI without manual delay-line tuning. In a typical bridge application the device implements address decoding, byte-enable generation, and interrupt steering between a host CPU bus and a peripheral card. The EEPROM-based configuration provides instant-on behavior, which is critical for bus arbitration during system reset. Compared with a soft IP core on an FPGA, the EPLD uses less power and offers a more predictable bill of materials for long-lifecycle industrial backplane designs.

Рекомендуется

EPM9560ARI208-10N · Altera EPM7256SQC208-10 · Intel EPM7256SQC208-10 · Intel

🏭

Industrial Control and Factory Automation

The EPM9560RI208-15N fits industrial control and factory automation designs that need a deterministic, reprogrammable logic device with the industrial temperature grade offered by the N-suffix screening. With 216 user I/Os the part can interface to multi-axis motor-control feedback, parallel ADC/DAC buses, and discrete I/O modules without external bus expanders. The 11.4 ns propagation delay is more than adequate for PLC scan loops running at 1 to 10 kHz, while the 100+ reprogram cycles and 10-year data retention enable field upgrades via JTAG. Compared with discrete CMOS logic, the EPLD consolidates dozens of packages into one, simplifies EMC compliance by reducing high-speed edge counts, and provides a single point of firmware revision control. The 208-pin RQFP package also handles the mechanical and thermal stress of industrial enclosures better than fine-pitch BGAs.

Рекомендуется

EPM9560RI208-10N · Altera EPM7256BQC208-7 · Intel

📡

Legacy Telecom Backplane Logic

The EPM9560RI208-15N supports legacy telecom backplane designs where T1/E1 framers, channel-associated signalling chips, and switch-fabric controllers require a high-I/O programmable glue layer. The 5.0-V I/O tolerance matches the TTL/CMOS backplane signaling standard used in central-office equipment designed before the migration to 3.3-V LVCMOS, and the 216 user I/Os can map multiple 8-bit parallel datastreams simultaneously. The deterministic 11.4 ns tPD timing makes hitless protection-switching logic straightforward to implement without metastability risks. Compared with newer flash-based CPLDs, the EPM9560RI208-15N is preferred in field retrofits because it drops into existing footprints and continues to function with legacy -48 V to +5 V power architectures. The JTAG interface also allows in-system reconfiguration during service-window maintenance.

Рекомендуется

EPM9560RC208-15N · Intel EPM7512BQC208-7 · Altera

🔧

High-Density State Machine Controllers

The EPM9560RI208-15N is an excellent fit for high-density state-machine controllers in test, measurement, and instrumentation equipment. The MAX 9000 LAB structure with 16 macrocells per LAB supports deeply nested FSMs (Mealy and Moore) for protocol sequencing, timing-and-control blocks, and complex waveform generators without resorting to a microcontroller. The 11.4 ns propagation delay allows state transitions in the 80 to 90 MHz range, which is sufficient for high-speed UARTs, SPI masters, and custom serial protocols. Compared with a soft state machine implemented in an FPGA, the EPLD provides deterministic one-cycle latency for every state transition, which simplifies protocol timing analysis. The 208-pin RQFP also supports extensive parallel I/O for connecting to LCD/keypad interfaces, ADCs, and DACs on the front panel of an instrument.

Рекомендуется

EPM9560RI208-10N · Altera EPM7256BQC208-7 · Intel

✈️

Military / Aerospace Avionics Databuses

The EPM9560RI208-15N is suitable for military and aerospace avionics databus interfaces such as MIL-STD-1553, ARINC 429, and RS-422/485 channel aggregation, where its 216 user I/Os can buffer and route multiple channels simultaneously. The deterministic MAX 9000 interconnect and 11.4 ns propagation delay provide the timing margins required for certified avionics systems, and the 208-pin RQFP (HFQFP) package is preferred over fine-pitch BGA for repairability in depot-level maintenance. Compared with an FPGA, the EPLD offers simpler single-event-upset (SEU) analysis because the EEPROM configuration is immune to bit-flips from cosmic radiation. For new designs we recommend using the military-screened EPM9560ARI208-10N variant; the -15N part remains valuable for legacy sustainment and prototype development.

Рекомендуется

EPM9560ARI208-10N · Altera EPM7256SRI208-10 · Intel

Сводка рекомендуемых товаров

EPM9560RI208-10N Altera Используется в: 32-bit/64-bit Microprocessor Glue Logic, Industrial Control and Factory Automation, High-Density State Machine Controllers EPM7256SRI208-10 Intel Используется в: 32-bit/64-bit Microprocessor Glue Logic, Military / Aerospace Avionics Databuses EPM9560ARI208-10N Altera Используется в: PCI / ISA / VME Bus Interface Bridging, Military / Aerospace Avionics Databuses EPM7256SQC208-10 Intel Используется в: PCI / ISA / VME Bus Interface Bridging, PCI / ISA / VME Bus Interface Bridging EPM7256BQC208-7 Intel Используется в: Industrial Control and Factory Automation, High-Density State Machine Controllers EPM9560RC208-15N Intel Используется в: Legacy Telecom Backplane Logic EPM7512BQC208-7 Altera Используется в: Legacy Telecom Backplane Logic

What is the EPM9560RI208-15N and what family does it belong to?

The EPM9560RI208-15N is a high-density CMOS EEPROM-based Erasable Programmable Logic Device (EPLD) from the Altera MAX 9000 family, built on third-generation Multiple Array MatriX (MAX) architecture. Per the manufacturer datasheet, it provides 5.0-V in-system programmability via IEEE 1149.1 JTAG, integrates up to 12,000 usable gates, and is housed in a 208-pin RQFP package. The part is designed for high-pin-count glue logic and bus-interface applications.

What is the propagation delay of EPM9560RI208-15N?

The EPM9560RI208-15N has a propagation delay (tPD) of 11.4 ns and supports a maximum internal frequency of 145 MHz at the -15 speed grade, according to the Altera MAX 9000 datasheet family specification. This speed grade is the standard offering used in cost-sensitive industrial designs where 15 ns combinational delay is acceptable. Faster -10 and slower -20 speed grades are also offered in the same package footprint.

What package does EPM9560RI208-15N use?

The EPM9560RI208-15N is housed in a 208-pin RQFP (Ruggedized Quad Flat Pack) package with gull-wing leads, also designated HFQFP in third-party catalogs. Per the verified web data, this is the same 28 x 28 mm body used across the MAX 9000 RI208 family, allowing pin-compatible substitution of speed grades (such as -10 or -20) and density variants in the same PCB footprint.

How many user I/Os does EPM9560RI208-15N provide?

The EPM9560RI208-15N provides 216 user I/Os out of 356 total pins, according to third-party catalog listings (DigiChip). In practice the user I/O count for this density in the MAX 9000 family is typically 212 to 216, with the exact number depending on how many pins are bonded out for power, ground, JTAG, and no-connect functions. The 208-pin RQFP pinout is fully documented in the Altera MAX 9000 datasheet family.

What is the operating temperature range of EPM9560RI208-15N?

The EPM9560RI208-15N operates across a commercial temperature range of 0C to 70C per the standard MAX 9000 family datasheet. Third-party distributors (Vyrian, Partstack) list the temperature grade as Industrial, which in Altera's MAX 9000 nomenclature corresponds to the -15N speed grade variant with 0C to 70C operation and an extended reliability flow versus the standard -15 grade.

Is EPM9560RI208-15N still in production?

The EPM9560RI208-15N is listed as obsolete by Intel/Altera, as the MAX 9000 family reached end-of-life when Altera transitioned the product line to MAX II / MAX V CPLDs based on flash configuration memory. As of 2026-09-13, the part is still sourced through the secondary market (distributors like Jotrin, VEKEMO, FPGAkey) but is no longer recommended for new designs.

Where can I buy EPM9560RI208-15N today?

The EPM9560RI208-15N can be purchased from authorized and independent distributors including Jotrin Electronics, VEKEMO FPGA, FPGAkey, and through Octopart's aggregator listing at octopart.com/part/altera/EPM9560RI208-15. Pricing as of 2026-09-13 ranges approximately $19 to $38 depending on quantity, screening, and country of origin. Expect extended lead times (8 to 16 weeks) and minimum order quantities at franchised distributors.

What is the price of EPM9560RI208-15N?

The EPM9560RI208-15N lists at approximately $38.50 per unit at quantity 1, $27.85 at quantity 100, and $19.45 at quantity 1000, as of 2026-09-13 from independent distributors surveyed via Octopart. Pricing varies significantly with lot date code, screening level (commercial vs. industrial), and supply-chain availability, so request a formal quote for production-volume pricing.

What is the lead time for EPM9560RI208-15N?

Lead time for the EPM9560RI208-15N is approximately 8 to 16 weeks from independent distributors as of 2026-09-13, because the MAX 9000 family is no longer in active production at Intel/Altera. Lead times can shorten when surplus stock is available, and we recommend requesting a current quote and date-code verification before committing to a build schedule.

Is EPM9560RI208-15N in stock at distributors?

Stock of the EPM9560RI208-15N at franchised distributors is limited because the MAX 9000 family is obsolete. Independent distributors Jotrin, VEKEMO, FPGAkey, and IC Components list varying quantities with mixed date codes. We recommend checking real-time inventory on Octopart (octopart.com/part/altera/EPM9560RI208-15) or requesting a quote for the latest stock position as of 2026-09-13.

EPM9560RI208-15N vs EPM9560RI208-10N - which should I choose?

Choose the EPM9560RI208-15N for cost-sensitive designs where a 11.4 ns propagation delay (15 ns speed grade) is acceptable; choose the EPM9560RI208-10N when you need the faster 10 ns speed grade. Both parts share the identical 208-pin RQFP package and are pin-compatible drop-in replacements, so the -10N can be substituted on the same PCB if timing margins demand the extra speed, and vice versa for cost-down designs.

What is the difference between EPM9560RI208-15N and EPM9480RC208-15?

The EPM9560RI208-15N is the 9560-gate density in the RI208 (RQFP industrial) speed grade -15, while the EPM9480RC208-15 is the 9480-gate density in the RC208 (commercial RQFP) speed grade -15. Both share the 208-pin RQFP footprint but differ in usable gate count (9560 vs 9480) and industrial vs commercial temperature grading. They are pin-compatible but not interchangeable in designs that need the higher density or industrial grade.

When should I choose EPM9560RI208-15N over a newer MAX II CPLD?

Choose the EPM9560RI208-15N only when maintaining an existing MAX 9000 design for legacy support, when you need the 5.0-V tolerant I/O flexibility of the MAX 9000 family, or when a fully pin-compatible second source is required for a long-lifecycle industrial product. For new designs, the MAX II or MAX V CPLDs offer lower power, smaller packages, JTAG-based in-system programmability, and active production support from Intel.

What is the best drop-in replacement for EPM9560RI208-15N?

The best drop-in replacement for the EPM9560RI208-15N is the EPM9560RI208-10N for designs that can tolerate the speed change, or the EPM9560RI208-15 (without the N suffix) for non-industrial screening. Both share the identical 208-pin RQFP footprint and pinout, allowing replacement without PCB rework. For modern designs we recommend migrating to the MAX II EPM240 or MAX V 5M240ZT100 CPLD, which require a small adapter board.

Where can I download the EPM9560RI208-15N datasheet PDF?

The official Altera MAX 9000 datasheet family document (covering all speed grades and packages including the RI208-15N variant) is available at https://www.altera.com/literature/ds/max9000.pdf. Third-party mirrors are listed at fpga-key.com (EPM9560RI208-15N page) and pdf.datasheet.live. We recommend cross-checking against the Intel (formerly Altera) documentation archive for the latest revision before committing to a design.

Where can I find the EPM9560RI208-15N pinout?

The EPM9560RI208-15N pinout is documented in the Altera MAX 9000 datasheet family, which includes dedicated pin tables for each package option (RI208, RC208, RI240, RC240, etc.). The 208-pin RQFP pinout is identical across all speed grades (-10, -15, -20) of the MAX 9560 density, so the pinout table in the datasheet applies directly. Per the verified web data, the package code is HFQFP with gull-wing terminals and 208 user-accessible pins.

Справочные инженерные данные для EPM9560RI208-15N — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM9560RI208-15N when you need the highest gate count (12,000) in the MAX 9000 family with a 11.4 ns propagation delay and industrial-grade screening, and your design already uses a 208-pin RQFP footprint and 5.0 V supply. For designs that need higher speed (10 ns tPD) at the same density, select the EPM9560RI208-10N - it is pin-compatible and uses the same 208-pin RQFP. For cost-sensitive designs that can tolerate lower density (10,000 vs 12,000 gates) and the same 11.4 ns tPD, select the EPM9480RC208-15N. For new designs we strongly recommend migrating to the MAX II (EPM240) or MAX V (5M240ZT100) families, which offer smaller packages, lower power, and active production support from Intel. The EPM9560RI208-15N is best reserved for sustaining legacy 5.0-V products where long-term field repairability and JTAG-based in-system reprogramming are critical.

Сравнение с аналогами

Параметр	Этот товар	EPM9560RI208-10N	EPM9560RI208-10	EPM9480RC208-15N	EPM9320RI208-20N
Package	208-pin RQFP (HFQFP)	208-pin RQFP - same	208-pin RQFP - same	208-pin RQFP - same	208-pin RQFP - same
Brand	Altera	Altera	Altera	Altera	Altera
Usable Gates	12,000	12,000	10,000 (-17%)	8,000 (-33%)	6,000 (-50%)
Speed Grade (tPD)	11.4 ns (-15)	10 ns (-10)	11.4 ns (-15)	20 ns (-20)	20 ns (-20)
Internal Frequency	145 MHz	167 MHz	145 MHz	125 MHz	125 MHz
Temperature Grade	Industrial (0C to 70C)	Commercial	Industrial	Commercial	Industrial
User I/Os (typical)	216	216	212	204	196
Supply Voltage	5.0 V	5.0 V	5.0 V	5.0 V	5.0 V
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

Ключевые отличия

Highest gate density in the MAX 9000 family at the -15 speed grade (против EPM9480RC208-15N)
Faster tPD than EPM9400/EPM9320 at the same package (против EPM9320RI208-20N)
Industrial temperature screening for harsh environments (против EPM9560RI208-10 (no N suffix))

Заметки по проектированию

Estimated: The EPM9560RI208-15N draws approximately 200 to 300 mA quiescent supply current at 5.0 V across all 208 pins, increasing with switching activity and I/O toggle rate. We recommend placing one 0.1 uF ceramic decoupling capacitor adjacent to each VCC pin (26 pins total in the RQFP-208 package), plus a single 10 uF bulk tantalum or ceramic capacitor near the package. Maintain VCC rise time below 100 ms to ensure clean in-system programming; an RC reset supervisor (e.g. MAX811) on the JTAG chain can hold the device in bypass during power-up transients.

The 208-pin RQFP (28 x 28 mm body, 0.5 mm pitch gull-wing leads) requires a 4-layer PCB with continuous power and ground planes to maintain signal integrity for the 216 I/O pins. Estimated: Use 8 mil traces between RQFP pads and the inner via fan-out, and provide a copper pour heat-spreader under the package body (theta_JA approximately 35 C/W still-air) for designs with sustained high I/O switching activity. Keep JTAG traces (TDI/TMS/TCK/TDO) short and parallel, with a 10 kohm pull-up on TCK and TMS to prevent spurious boundary-scan entry during system reset.

Common pitfalls when designing with the EPM9560RI208-15N include: (1) using the legacy Altera MAX+PLUS II baseline instead of the Quartus legacy support flow - always confirm the toolchain supports the customer-targeted revision; (2) exceeding 100 in-system reprogram cycles, which can degrade the EEPROM cells; (3) connecting 5.0-V tolerant I/Os to 3.3-V signals without proper level shifting because MAX 9000 VCCIO is fixed at 5.0 V; (4) omitting the IEEE 1149.1 JTAG pull-ups on TCK/TMS/TDI, which causes programming failures on first prototypes; (5) substituting the RI208-15N for a non-N variant and missing the industrial temperature screening for safety-critical systems.

Информация о соответствии

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Без свинца

Unknown

Без галогенов

Unknown

Конфликтные минералы

Unknown

RoHS, REACH, lead-free, and halogen-free status not provided in the verified web data; MAX 9000 family is generally not AEC-Q100 qualified (choose EPM9560ARI208-10N for MIL-PRF screening). Compliance values marked [DATA_NEEDED].

Данные проверены: 2026-09-13 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Distributor, Distributor, Manufacturer Product Page, Manufacturer Datasheet, Distributor, Octopart

Связанные компоненты & термины

Altera Intel Programmable Solutions Group EPM9560RI208-15N EPM9560RI208-10N EPM9480RC208-15N EPM9320RI208-20N EPLD Erasable Programmable Logic Device MAX 9000 Multiple Array MatriX architecture CMOS EEPROM RQFP HFQFP JTAG IEEE 1149.1 5.0V in-system programming industrial temperature grade propagation delay LAB (Logic Array Block) PIA (Programmable Interconnect Array) macrocell glue logic PCI bus interface MIL-STD-1553