EP3SE260H780C3N vs EP3SE260H780C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260H780C3N sa pamamagitan ng Intel at EP3SE260H780C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3SE260H780C3N | EP3SE260H780C4N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Series | Stratix® III E | — |
| Logic Elements (LE) | 255,000 | — |
| Embedded Memory (bits) | 16,672,768 | — |
| Number of LABs/CLBs | 10,200 | — |
| User I/Os | 488 | — |
| Number of Pins / Balls | 780 | — |
| Packhaging | 780-BBGA, FCBGA (H780) | 780-ball FCBGA (Flip Chip BGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 °C to +85 °C (C grade, commercial) | 0C to +85C (commercial) |
| Process Technology | 40 nm CMOS | — |
| Maximum Core Frequency | [DATA_NEEDED: maximum core frequency MHz] | — |
| Supply Voltage (VCCINT) | [DATA_NEEDED: VCCINT nominal V] | — |
| Transceivers | [DATA_NEEDED: number of embedded transceivers and max data rate] | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks and precision] | — |
| Tindminan RoHS | Compliant (lead-free 'N' suffix) | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | 3 (168 hours) |
| Configuration Method | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel | Serial/Parallel via Quartus II |
| Design Toolchain | Altera Quartus II (legacy); Intel Quartus Prime | — |
| Family | — | Stratix III E (Enhanced) |
| Logic Elements | — | 255,000 |
| Logic Array Blocks (LABs) | — | 10,200 |
| Total RAM Bits | — | 16,672,768 |
| Embedded Memory | — | M9K and M144K blocks |
| User I/O Pins | — | 488 |
| DSP Blocks (18x18 Multipliers) | — | 768 |
| PLLs | — | 12 |
| Process Node | — | 65 nm CMOS |
| Core Voltage | — | 0.86 V to 1.15 V |
| Maximum Core Clock Frequency | — | 450 MHz |