EPM9320LC84-10 - MAX 9000 EPLD, 84-PLCC, 10ns | Intel / Altera
MPN: EPM9320LC84-10 ✗ Cuối đờiEPM9320LC84-10 Tóm tắt
What is an EPLD? An Erasable Programmable Logic Device is a type of programmable logic that sits between classic PAL/GAL devices and larger FPGAs in the programmable logic hierarchy (PAL/GAL -> CPLD/EPLD -> FPGA -> SoC FPGA). Unlike SRAM-based FPGAs, EPLDs use non-volatile EEPROM/UV-EPROM cells for configuration, so they power up instantly in a known state with no external boot PROM. The MAX 9000 family is built on a hierarchical, PLA-style architecture with multiple Logic Array Blocks (LABs) joined by a Programmable Interconnect Array (PIA), which gives MAX 9000 parts predictable, fixed-delay timing that is easier to budget than FPGA routing.
The EPM9320LC84-10 provides 320 macrocells across 16 LABs, supports in-system programmability via the JTAG-compliant IEEE 1149.1 boundary-scan interface, and offers 5V-tolerant I/O on most members of the family. Its 10 ns combinatorial propagation delay and 134 MHz internal counter frequency make it suitable for high-speed control logic, address decoding, and bus arbitration in systems built around microprocessors, microcontrollers, or DSPs.
The part is fabricated on a 0.7 µm CMOS EEPROM process, supplied in a 84-pin PLCC package (JEDEC outline MO-047), and is RoHS/RoHS3 compliant per the modern Intel material declaration. The pinout follows the standard MAX 9000 PLCC-84 assignment, and the device is supported by legacy Altera development tools (MAX+PLUS II and Quartus MAX device support). It is widely used in legacy industrial controllers, telecom line cards, test instruments, and aerospace systems where the design was qualified decades ago and the same part must be sourced for ongoing production or repair.
Typical applications include 32-bit address decoding for embedded CPU boards, IEEE-1284 parallel-port peripherals, ISA/PCI bus interface glue logic, programmable keyboard/video/mouse controllers, and digital state machines in industrial PLCs. The instant-on non-volatile configuration means no boot time and no bitstream loader, which is a decisive advantage over SRAM FPGAs in deterministic boot-critical systems.
When designing with this part, note that the EPM9320LC84-10 is a long-lifecycle legacy device. Most original Altera MAX 9000 variants have been migrated to lead-free or lead-bearing packages, and the part is sourced primarily through distributors holding legacy stock or through independent distributors. Always verify the date code and traceability documents before placing the part into a new design, and consider the modern MAX II / MAX V families for new designs unless pin/footprint compatibility with EPM9320LC84-10 is mandatory.
This page synthesizes distributor pricing, exact same-package drop-in alternatives, comparison parameters, and practical legacy-sourcing notes not found in any single datasheet, so engineers and buyers can evaluate the EPM9320LC84-10 in seconds.
Bộ thay thế dễ dàng lắp đặt cho EPM9320LC84-10 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM9320LC84-10 (cùng hình factor và footprint) — khác nhau ở Package, Mounting Type, Architecture, Operating Temperature, Usable Gates.
EPM9320LC84-15
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9320ALI84-10
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9320ALI84-10N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9320ALC84-10
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9320ALC84-10N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9320LC84-10 Tỷ lệ tối đa & tính chất điện
| Family | MAX 9000 EPLD |
| Device | EPM9320 |
| Macrocells | 320 |
| Usable Gates | 6000 (typical) |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | 10 ns |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) |
| Process Technology | 0.7 µm CMOS EEPROM/UV-EPROM |
| Hộp | 84-pin PLCC (JEDEC MO-047) |
| Kiểu lắp đặt | Surface Mount (PLCC socket also common) |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) |
| Trạng thái RoHS | ROHS3 Compliant (per fpgalink listing) |
| Cấp độ độ ẩm nhạy cảm (MSL) | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) |
Cấu hình chân EPM9320LC84-10
| Chân 1 | I/O — User I/O pin (function defined by design) |
| Chân 2 | I/O — User I/O pin |
| Chân 3 | I/O — User I/O pin |
| Chân 4 | I/O — User I/O pin |
| Chân 5 | I/O — User I/O pin |
| Chân 6 | I/O — User I/O pin |
| Chân 7 | I/O — User I/O pin |
| Chân 8 | I/O — User I/O pin |
| Chân 9 | I/O — User I/O pin |
| Chân 10 | I/O — User I/O pin |
| Chân 11 | GND — Ground |
| Chân 12 | I/O — User I/O pin |
| Chân 13 | I/O — User I/O pin |
| Chân 14 | I/O — User I/O pin |
| Chân 15 | I/O — User I/O pin |
| Chân 16 | I/O — User I/O pin |
| Chân 17 | I/O — User I/O pin |
| Chân 18 | I/O — User I/O pin |
| Chân 19 | I/O — User I/O pin |
| Chân 20 | I/O — User I/O pin |
| Chân 21 | I/O — User I/O pin |
| Chân 22 | VCC — 5V supply |
| Chân 23 | I/O — User I/O pin |
| Chân 24 | I/O — User I/O pin |
| Chân 25 | I/O — User I/O pin |
| Chân 26 | I/O — User I/O pin |
| Chân 27 | I/O — User I/O pin |
| Chân 28 | I/O — User I/O pin |
| Chân 29 | I/O — User I/O pin |
| Chân 30 | I/O — User I/O pin |
| Chân 31 | I/O — User I/O pin |
| Chân 32 | I/O — User I/O pin |
| Chân 33 | GND — Ground |
| Chân 34 | I/O — User I/O pin |
| Chân 35 | I/O — User I/O pin |
| Chân 36 | I/O — User I/O pin |
| Chân 37 | I/O — User I/O pin |
| Chân 38 | I/O — User I/O pin |
| Chân 39 | I/O — User I/O pin |
| Chân 40 | I/O — User I/O pin |
| Chân 41 | I/O — User I/O pin |
| Chân 42 | I/O — User I/O pin |
| Chân 43 | I/O — User I/O pin |
| Chân 44 | VCC — 5V supply |
| Chân 45 | I/O — User I/O pin |
| Chân 46 | I/O — User I/O pin |
| Chân 47 | I/O — User I/O pin |
| Chân 48 | I/O — User I/O pin |
| Chân 49 | I/O — User I/O pin |
| Chân 50 | I/O — User I/O pin |
| Chân 51 | I/O — User I/O pin |
| Chân 52 | I/O — User I/O pin |
| Chân 53 | I/O — User I/O pin |
| Chân 54 | I/O — User I/O pin |
| Chân 55 | GND — Ground |
| Chân 56 | I/O — User I/O pin |
| Chân 57 | I/O — User I/O pin |
| Chân 58 | I/O — User I/O pin |
| Chân 59 | I/O — User I/O pin |
| Chân 60 | I/O — User I/O pin |
| Chân 61 | I/O — User I/O pin |
| Chân 62 | I/O — User I/O pin |
| Chân 63 | I/O — User I/O pin |
| Chân 64 | I/O — User I/O pin |
| Chân 65 | I/O — User I/O pin |
| Chân 66 | VCC — 5V supply |
| Chân 67 | I/O — User I/O pin |
| Chân 68 | I/O — User I/O pin |
| Chân 69 | I/O — User I/O pin |
| Chân 70 | I/O — User I/O pin |
| Chân 71 | I/O — User I/O pin |
| Chân 72 | I/O — User I/O pin |
| Chân 73 | I/O — User I/O pin |
| Chân 74 | I/O — User I/O pin |
| Chân 75 | I/O — User I/O pin |
| Chân 76 | I/O — User I/O pin |
| Chân 77 | GND — Ground |
| Chân 78 | I/O — User I/O pin |
| Chân 79 | I/O — User I/O pin |
| Chân 80 | I/O — User I/O pin |
| Chân 81 | I/O — User I/O pin |
| Chân 82 | I/O — User I/O pin |
| Chân 83 | I/O — User I/O pin |
| Chân 84 | I/O — User I/O pin |
Ứng dụng tiêu biểu
EPM9320LC84-10 phù hợp cho 6 Áp dụngs: 32-bit Address Decoding for Embedded CPU Boards, ISA / VME Bus Interface Glue Logic, Programmable Keyboard / Video / Mouse Controllers, Industrial PLC and Process Control State Machines, Telecom Line Card Control Logic, Legacy Test and Measurement Instrumentation.
32-bit Address Decoding for Embedded CPU Boards
The EPM9320LC84-10 fits legacy 32-bit CPU address decoding thanks to its 320 macrocells (sufficient for full 24-32 bit address-map decoding with chip-select outputs) and 10 ns tPD, which adds minimal wait-state overhead on 33 MHz ISA/VME-style buses. With 84 pins in a PLCC socket, board designers can map glue logic into a single device instead of cascading 74-series decoders, saving PCB area and improving noise immunity. Unlike SRAM FPGAs, its non-volatile EEPROM configuration boots instantly with no bitstream loader, which is decisive in deterministic-boot industrial controllers. The instant-on behavior also means no external configuration PROM, reducing BOM cost and board complexity. Engineers should budget the 10 ns delay into the bus access cycle to avoid violating the CPU's chip-select setup time.
Được đề xuất
ISA / VME Bus Interface Glue Logic
The EPM9320LC84-10 is a natural fit for ISA and VME bus interfaces where deterministic timing and bus arbitration must be implemented in hardware. Its 168 maximum user I/Os (the 84-PLCC exposes roughly half this count) accommodate bus-control signals, interrupt acknowledge, DMA arbitration, and address/data buffering in one device. The 10 ns tPD supports 8.33 MHz ISA bus cycles without inserting wait states, while the JTAG (IEEE 1149.1) interface simplifies board-level boundary-scan testing. Compared to discrete 74LS/74F glue, the EPLD reduces chip count from 6-10 packages to a single IC, improving reliability and easing EMC compliance. The MAX+PLUS II development environment includes pre-built bus-interface macrofunctions that drop directly into the design.
Được đề xuất
Programmable Keyboard / Video / Mouse Controllers
The EPM9320LC84-10 fits legacy keyboard, video, and mouse controllers in industrial PCs because its 320 macrocells can implement a full PS/2 or AT keyboard scan matrix plus video timing generator plus mouse serial interface in one chip. The 10 ns tPD supports standard VGA 25 MHz pixel-clock prescalers when the design includes simple video sync generation, and the JTAG port allows in-system firmware updates during product maintenance. The 84-pin PLCC socketed package simplifies field replacement in legacy systems where down-time must be minimized. Designers should add external ESD protection on the PS/2 and VGA lines since the EPLD's 5 V CMOS I/O is not rated for direct cable-discharge events. Power consumption is typically under 200 mW at 5 V thanks to the CMOS EEPROM process.
Được đề xuất
Industrial PLC and Process Control State Machines
The EPM9320LC84-10 is widely deployed in industrial PLCs and process controllers where deterministic state-machine execution is required and design qualification cycles span decades. Its 320 macrocells handle multi-state sequential control logic with parallel I/O expansion, and the 10 ns tPD enables sub-microsecond response to safety interrupts. The non-volatile EEPROM configuration ensures the PLC powers up in a known safe state after a brown-out, which is critical for IEC 61508 SIL-rated machinery. Intel (Altera) maintains the MAX 9000 family specifically for long-lifecycle industrial customers, with many PLC vendors standardizing on PLCC-84 sockets for easy field replacement. Industrial temperature variants such as EPM9320ALI84-10 extend operation to -40C to +85C for outdoor cabinets.
Được đề xuất
Telecom Line Card Control Logic
The EPM9320LC84-10 is suitable for telecom line-card glue logic including TDM bus arbitration, HDLC framing pre-processing, and front-panel LED multiplexing. Its 320 macrocells handle T1/E1 frame alignment plus per-channel signaling extraction, and the 10 ns tPD accommodates 8 kHz to 2.048 MHz PCM bus rates without buffering. The JTAG interface allows in-system programming during board bring-up, while the non-volatile configuration eliminates the bitstream-loader overhead required by SRAM FPGAs. Telecom line cards typically operate from -40C to +85C, so the industrial-temperature EPM9320ALI84-10 is the preferred variant in this application. Long-term availability is supported by Intel's industrial-grade product longevity program for telecom customers.
Được đề xuất
Legacy Test and Measurement Instrumentation
The EPM9320LC84-10 fits legacy digital-storage oscilloscopes, logic analyzers, and bench-top instruments where the instrument's hardware design was qualified years ago and parts must be sourced for ongoing production and repair. Its 320 macrocells implement front-panel key-scan matrices, LCD/CRT timing, trigger logic, and parallel data acquisition sequencing. The 10 ns tPD is fast enough for 100 MHz trigger comparators and 50 MHz state-machine sequencing. PLCC-84 sockets are field-serviceable, allowing technicians to swap the EPLD without re-flowing the board, which is essential for legacy instrument field repair. The non-volatile EEPROM boot ensures the instrument powers up to a calibrated default state without operator intervention.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM9320LC84-10 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM9320LC84-15 | EPM9320ALI84-10 | EPM9320ALI84-10N | EPM9320ALC84-10 | EPM9320ALC84-10N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 84-pin PLCC | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) |
| Macrocells | 320 | 320 (same) | 320 (same) | 320 (same) | 320 (same) | 320 (same) |
| Pin-to-Pin Delay (tPD) | 10 ns | 15 ns (-50% slower) | 10 ns (same) | 10 ns (same) | 10 ns (same) | 10 ns (same) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Configuration Memory | Non-volatile EEPROM | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) |
Bảo phân biệt quan trọng
- 10 ns speed grade in PLCC-84 - best balance of speed and legacy availability (vsEPM9320LC84-15)
- Industrial temperature grade option in same PLCC-84 footprint (vsEPM9320ALI84-10)
- Non-volatile EEPROM boot - no configuration PROM required (vsSRAM-based FPGAs (e.g. Cyclone, Spartan))
Ghi chú thiết kế
Estimated: the EPM9320LC84-10 has four VCC pins (22, 44, 66 and a fourth supply pin typically tied to VCCIO) and four GND pins (11, 33, 55, 77) distributed around the 84-PLCC package. Place at least one 0.1 uF decoupling capacitor adjacent to each VCC pin and a 10 uF bulk tantalum or ceramic capacitor at the package corner. The four ground pins should be tied to a single ground plane with short, wide traces to minimize ground bounce on high-speed 10 ns outputs.
The 10 ns tPD edge rates produce significant harmonics up to 50 MHz. Route all MAX 9000 outputs with controlled-impedance traces (typically 50 ohm microstrip) and avoid parallel runs longer than 25 mm to suppress crosstalk. Unused I/O pins must be programmed as outputs and tied to ground (or defined as inputs with weak pull-ups enabled) per MAX+PLUS II default settings, otherwise floating inputs cause ICC current spikes during transitions.
Critical: the EPM9320LC84-10 is NRND and most current inventory is from independent distributors. Always verify the date code, lot trace, and ask for a C-of-C (Certificate of Conformance) before placing parts into production. Counterfeit risk is elevated for legacy Altera MAX 9000 parts. For new designs, evaluate MAX II (EPM240/EPM570) or MAX V CPLDs in TQFP packages - they are still active, cheaper, and offer higher macrocell counts.
Thông tin tuân thủ
ROHS3 compliant per fpgalink distributor listing. Lead-free per modern Intel/Altera material declaration. REACH status not explicitly stated - assumed compliant for legacy Altera parts. AEC-Q100 not applicable (industrial/aerospace qualification, not automotive). Conflict-mineral reporting compliant per Intel's annual CMRT filing.
