Altera
EPM9560RC208-19 - MAX 9000 CPLD, 560 Macrocells, 19ns | Altera
MPN: EPM9560RC208-19 ✗ Cuối đời
5.0 V Vdss
RQFP-208 (208-pin PQFP) Package
MOQ: 1 |
EPM9560RC208-19 Tóm tắt
The Altera EPM9560RC208-19 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, featuring 560 macrocells, 12,000 usable gates, and a pin-to-pin propagation delay of 19 ns, housed in a 208-pin RQFP package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, the device provides 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface, enabling boundary-scan test, in-system configuration, and rapid prototyping without external programmers.
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with high-density macrocell fabric and deterministic timing. Within the broader programmable logic hierarchy, CPLDs sit below FPGAs in density but above simple PLDs in logic capacity, offering instant-on behavior, single-chip solutions, and predictable routing delays that make them ideal for glue logic, bus interface, and state-machine replacement roles.
Key features of the EPM9560RC208-19 include 772 flip-flops, 149 user I/O pins, 5-V tolerant I/O with multi-voltage interface support, JTAG-compliant ISP, and a maximum toggle frequency that supports high-speed control logic. The 208-pin RQFP (also called PQFP) package provides a generous I/O count for system integration while retaining a manageable footprint for production assembly. The -19 speed grade designates the 19 ns propagation delay bin.
Technical depth: the MAX 9000 architecture uses a programmable interconnect array (PIA) that routes signals between Logic Array Blocks (LABs), giving every signal a consistent and predictable delay regardless of placement. This deterministic timing eliminates the place-and-route iterations often required by FPGAs. The EEPROM-based configuration cell is non-volatile, so the device powers up instantly in its programmed state with no external boot memory required.
Typical applications include bus interfacing (PCI, ISA, VME), state-machine replacement, address decoding and glue logic in microprocessor systems, peripheral control, and high-volume glue-logic consolidation. The wide I/O count makes it particularly suited to 32-bit and 64-bit system bus bridging tasks.
Design consideration: when migrating a MAX 9000 design to a newer family, verify that the pinout and JTAG programming flow are compatible. The RQFP-208 footprint differs from later BGA-packaged MAX II/MAX V devices, so PCB redesign is generally required.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, providing engineers with a single reference for the EPM9560RC208-19 across sourcing, design, and lifecycle decisions.
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with high-density macrocell fabric and deterministic timing. Within the broader programmable logic hierarchy, CPLDs sit below FPGAs in density but above simple PLDs in logic capacity, offering instant-on behavior, single-chip solutions, and predictable routing delays that make them ideal for glue logic, bus interface, and state-machine replacement roles.
Key features of the EPM9560RC208-19 include 772 flip-flops, 149 user I/O pins, 5-V tolerant I/O with multi-voltage interface support, JTAG-compliant ISP, and a maximum toggle frequency that supports high-speed control logic. The 208-pin RQFP (also called PQFP) package provides a generous I/O count for system integration while retaining a manageable footprint for production assembly. The -19 speed grade designates the 19 ns propagation delay bin.
Technical depth: the MAX 9000 architecture uses a programmable interconnect array (PIA) that routes signals between Logic Array Blocks (LABs), giving every signal a consistent and predictable delay regardless of placement. This deterministic timing eliminates the place-and-route iterations often required by FPGAs. The EEPROM-based configuration cell is non-volatile, so the device powers up instantly in its programmed state with no external boot memory required.
Typical applications include bus interfacing (PCI, ISA, VME), state-machine replacement, address decoding and glue logic in microprocessor systems, peripheral control, and high-volume glue-logic consolidation. The wide I/O count makes it particularly suited to 32-bit and 64-bit system bus bridging tasks.
Design consideration: when migrating a MAX 9000 design to a newer family, verify that the pinout and JTAG programming flow are compatible. The RQFP-208 footprint differs from later BGA-packaged MAX II/MAX V devices, so PCB redesign is generally required.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, providing engineers with a single reference for the EPM9560RC208-19 across sourcing, design, and lifecycle decisions.
Bộ thay thế dễ dàng lắp đặt cho EPM9560RC208-19 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM9560RC208-19 (cùng hình factor và footprint) — khác nhau ở Package, Device Type, Propagation Delay (tPD), Configuration Memory, User I/O Pins.
Altera
Package: 208-pin RQFP (Power Quad Flat Pack)
Device Type: EEPROM-based Complex Programmable Logic Device (CPLD)
So sánh với EPM9560RC208-19 →
Altera
Package: 208-pin RQFP
Device Type: EEPROM-based CPLD (EPLD)
Propagation Delay (tPD): 15 ns
So sánh với EPM9560RC208-19 →
Intel
Package: 208-pin RQFP (Power Quad Flat Pack)
Device Type: CPLD (Complex Programmable Logic Device)
Configuration Memory: CMOS EEPROM (non-volatile)
So sánh với EPM9560RC208-19 →
Altera
Package: 208-pin RQFP (Power Quad Flat Pack)
Propagation Delay (tPD): 18 ns (speed grade -18)
Configuration Memory: EEPROM (non-volatile, no external config PROM)
So sánh với EPM9560RC208-19 →
Altera
Package: 208-pin RQFP (Power Quad Flat Pack)
Device Type: EEPROM-based CPLD (EE PLD)
Propagation Delay (tPD): 20 ns (speed grade -20)
So sánh với EPM9560RC208-19 →
EPM9560RC208-15
✅ Drop-In ⚠️ Thông số chưa được xác minhAltera
📦 RQFP-208
MAX 9000 · EEPROM-based Complex Programmable Logic Device (CPLD) · 12,000 gates · 560 macro cells · 15 ns · 117.6 MHz · 5.0 V · EEPROM (non-volatile)
Liên hệ để biết giá
Xem tài liệu →EPM9560RC208-17
✅ Drop-In ⚠️ Thông số chưa được xác minhAltera
📦 RQFP-208
MAX 9000 · CPLD (EPLD, in-system programmable) · 12,000 · 560 · 16 · 17 ns · 117.6 MHz · 212
Liên hệ để biết giá
Xem tài liệu →EPM9560RC208-18
✅ Drop-In ⚠️ Thông số chưa được xác minhAltera
📦 RQFP-208
MAX 9000 (EPM9560) · EEPROM-based Complex Programmable Logic Device (CPLD) · 12,000 gates · 560 macrocells · 18 ns (speed grade -18) · 117.6 MHz (family -15 grade reference) · 5 V · 3.3 V or 5 V
Liên hệ để biết giá
Xem tài liệu →EPM9560RC208-20
✅ Drop-InIntel
📦 RQFP-208
MAX 9000 (EPM9560) · 560 · 12,000 · 35 · 153 · 20 ns · 100 MHz · 5.0 V
Liên hệ để biết giá
Xem tài liệu →EPM9560RC208-20C
✅ Drop-InAltera
📦 RQFP-208
MAX 9000 · EEPROM-based CPLD (EE PLD) · 560 · 12,000 · 772 · 149 · 20 ns (speed grade -20) · 100 MHz
Liên hệ để biết giá
Xem tài liệu →EPM9560RC208-15N
✅ Drop-In ⚠️ Thông số chưa được xác minhIntel
📦 RQFP-208
MAX 9000 · CPLD (Complex Programmable Logic Device) · 560 · 12,000 · 16 · 212 (in 208-RQFP, see family datasheet) · 15 ns · 117.6 MHz
Liên hệ để biết giá
Xem tài liệu →EPM9560RC208-15C
✅ Drop-In ⚠️ Thông số chưa được xác minhAltera
📦 RQFP-208
MAX 9000 · EEPROM-based CPLD (EPLD) · 12,000 · 560 · 149 · 15 ns · 117.6 MHz · 4.75 V to 5.25 V
Liên hệ để biết giá
Xem tài liệu →EPM9560RC208-19 Tỷ lệ tối đa & tính chất điện
| Device Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Flip-Flops | 772 |
| User I/O Pins | 149 |
| Propagation Delay (tPD) | 19 ns |
| Supply Voltage (VCCINT) | 5.0 V |
| I/O Voltage Tolerance | 3.3 V / 5 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Technology | CMOS EEPROM |
| Hộp | RQFP-208 (208-pin PQFP) |
| JEDEC Package Code | S-PQFP-G208 |
| Kiểu lắp đặt | Surface Mount |
Cấu hình chân EPM9560RC208-19
| Chân 1 | I/O — User I/O pin (bank 1) |
| Chân 2 | I/O — User I/O pin (bank 1) |
| Chân 3 | I/O — User I/O pin (bank 1) |
| Chân 4 | I/O — User I/O pin (bank 1) |
| Chân 5 | I/O — User I/O pin (bank 1) |
| Chân 6 | I/O — User I/O pin (bank 1) |
| Chân 7 | I/O — User I/O pin (bank 1) |
| Chân 8 | I/O — User I/O pin (bank 1) |
| Chân 9 | I/O — User I/O pin (bank 1) |
| Chân 10 | I/O — User I/O pin (bank 1) |
| Chân 11 | VCCIO1 — I/O supply voltage bank 1 (3.3V or 5V) |
| Chân 12 | I/O — User I/O pin (bank 1) |
| Chân 13 | I/O — User I/O pin (bank 1) |
| Chân 14 | I/O — User I/O pin (bank 1) |
| Chân 15 | I/O — User I/O pin (bank 1) |
| Chân 16 | I/O — User I/O pin (bank 1) |
| Chân 17 | I/O — User I/O pin (bank 1) |
| Chân 18 | I/O — User I/O pin (bank 1) |
| Chân 19 | I/O — User I/O pin (bank 1) |
| Chân 20 | I/O — User I/O pin (bank 1) |
| Chân 21 | GND — Ground |
| Chân 22 | I/O — User I/O pin (bank 2) |
| Chân 23 | I/O — User I/O pin (bank 2) |
| Chân 24 | I/O — User I/O pin (bank 2) |
| Chân 25 | I/O — User I/O pin (bank 2) |
| Chân 26 | I/O — User I/O pin (bank 2) |
| Chân 27 | I/O — User I/O pin (bank 2) |
| Chân 28 | I/O — User I/O pin (bank 2) |
| Chân 29 | I/O — User I/O pin (bank 2) |
| Chân 30 | I/O — User I/O pin (bank 2) |
| Chân 31 | I/O — User I/O pin (bank 2) |
| Chân 32 | I/O — User I/O pin (bank 2) |
| Chân 33 | VCCIO2 — I/O supply voltage bank 2 (3.3V or 5V) |
| Chân 34 | I/O — User I/O pin (bank 2) |
| Chân 35 | I/O — User I/O pin (bank 2) |
| Chân 36 | I/O — User I/O pin (bank 2) |
| Chân 37 | I/O — User I/O pin (bank 2) |
| Chân 38 | I/O — User I/O pin (bank 2) |
| Chân 39 | I/O — User I/O pin (bank 2) |
| Chân 40 | I/O — User I/O pin (bank 2) |
| Chân 41 | I/O — User I/O pin (bank 2) |
| Chân 42 | I/O — User I/O pin (bank 2) |
| Chân 43 | GND — Ground |
| Chân 44 | I/O — User I/O pin (bank 3) |
| Chân 45 | I/O — User I/O pin (bank 3) |
| Chân 46 | I/O — User I/O pin (bank 3) |
| Chân 47 | I/O — User I/O pin (bank 3) |
| Chân 48 | I/O — User I/O pin (bank 3) |
| Chân 49 | I/O — User I/O pin (bank 3) |
| Chân 50 | I/O — User I/O pin (bank 3) |
| Chân 51 | I/O — User I/O pin (bank 3) |
| Chân 52 | I/O — User I/O pin (bank 3) |
| Chân 53 | I/O — User I/O pin (bank 3) |
| Chân 54 | I/O — User I/O pin (bank 3) |
| Chân 55 | VCCIO3 — I/O supply voltage bank 3 (3.3V or 5V) |
| Chân 56 | I/O — User I/O pin (bank 3) |
| Chân 57 | I/O — User I/O pin (bank 3) |
| Chân 58 | I/O — User I/O pin (bank 3) |
| Chân 59 | I/O — User I/O pin (bank 3) |
| Chân 60 | I/O — User I/O pin (bank 3) |
| Chân 61 | I/O — User I/O pin (bank 3) |
| Chân 62 | I/O — User I/O pin (bank 3) |
| Chân 63 | I/O — User I/O pin (bank 3) |
| Chân 64 | I/O — User I/O pin (bank 3) |
| Chân 65 | GND — Ground |
| Chân 66 | I/O — User I/O pin (bank 4) |
| Chân 67 | I/O — User I/O pin (bank 4) |
| Chân 68 | I/O — User I/O pin (bank 4) |
| Chân 69 | I/O — User I/O pin (bank 4) |
| Chân 70 | I/O — User I/O pin (bank 4) |
| Chân 71 | I/O — User I/O pin (bank 4) |
| Chân 72 | I/O — User I/O pin (bank 4) |
| Chân 73 | I/O — User I/O pin (bank 4) |
| Chân 74 | I/O — User I/O pin (bank 4) |
| Chân 75 | I/O — User I/O pin (bank 4) |
| Chân 76 | I/O — User I/O pin (bank 4) |
| Chân 77 | VCCIO4 — I/O supply voltage bank 4 (3.3V or 5V) |
| Chân 78 | I/O — User I/O pin (bank 4) |
| Chân 79 | I/O — User I/O pin (bank 4) |
| Chân 80 | I/O — User I/O pin (bank 4) |
| Chân 81 | I/O — User I/O pin (bank 4) |
| Chân 82 | I/O — User I/O pin (bank 4) |
| Chân 83 | I/O — User I/O pin (bank 4) |
| Chân 84 | I/O — User I/O pin (bank 4) |
| Chân 85 | I/O — User I/O pin (bank 4) |
| Chân 86 | I/O — User I/O pin (bank 4) |
| Chân 87 | GND — Ground |
| Chân 88 | I/O — User I/O pin (bank 5) |
| Chân 89 | I/O — User I/O pin (bank 5) |
| Chân 90 | I/O — User I/O pin (bank 5) |
| Chân 91 | I/O — User I/O pin (bank 5) |
| Chân 92 | I/O — User I/O pin (bank 5) |
| Chân 93 | I/O — User I/O pin (bank 5) |
| Chân 94 | I/O — User I/O pin (bank 5) |
| Chân 95 | I/O — User I/O pin (bank 5) |
| Chân 96 | I/O — User I/O pin (bank 5) |
| Chân 97 | I/O — User I/O pin (bank 5) |
| Chân 98 | I/O — User I/O pin (bank 5) |
| Chân 99 | VCCIO5 — I/O supply voltage bank 5 (3.3V or 5V) |
| Chân 100 | I/O — User I/O pin (bank 5) |
| Chân 101 | I/O — User I/O pin (bank 5) |
| Chân 102 | I/O — User I/O pin (bank 5) |
| Chân 103 | I/O — User I/O pin (bank 5) |
| Chân 104 | I/O — User I/O pin (bank 5) |
| Chân 105 | I/O — User I/O pin (bank 5) |
| Chân 106 | I/O — User I/O pin (bank 5) |
| Chân 107 | I/O — User I/O pin (bank 5) |
| Chân 108 | I/O — User I/O pin (bank 5) |
| Chân 109 | GND — Ground |
| Chân 110 | I/O — User I/O pin (bank 6) |
| Chân 111 | I/O — User I/O pin (bank 6) |
| Chân 112 | I/O — User I/O pin (bank 6) |
| Chân 113 | I/O — User I/O pin (bank 6) |
| Chân 114 | I/O — User I/O pin (bank 6) |
| Chân 115 | I/O — User I/O pin (bank 6) |
| Chân 116 | I/O — User I/O pin (bank 6) |
| Chân 117 | I/O — User I/O pin (bank 6) |
| Chân 118 | I/O — User I/O pin (bank 6) |
| Chân 119 | I/O — User I/O pin (bank 6) |
| Chân 120 | I/O — User I/O pin (bank 6) |
| Chân 121 | VCCIO6 — I/O supply voltage bank 6 (3.3V or 5V) |
| Chân 122 | I/O — User I/O pin (bank 6) |
| Chân 123 | I/O — User I/O pin (bank 6) |
| Chân 124 | I/O — User I/O pin (bank 6) |
| Chân 125 | I/O — User I/O pin (bank 6) |
| Chân 126 | I/O — User I/O pin (bank 6) |
| Chân 127 | I/O — User I/O pin (bank 6) |
| Chân 128 | I/O — User I/O pin (bank 6) |
| Chân 129 | I/O — User I/O pin (bank 6) |
| Chân 130 | I/O — User I/O pin (bank 6) |
| Chân 131 | GND — Ground |
| Chân 132 | I/O — User I/O pin (bank 7) |
| Chân 133 | I/O — User I/O pin (bank 7) |
| Chân 134 | I/O — User I/O pin (bank 7) |
| Chân 135 | I/O — User I/O pin (bank 7) |
| Chân 136 | I/O — User I/O pin (bank 7) |
| Chân 137 | I/O — User I/O pin (bank 7) |
| Chân 138 | I/O — User I/O pin (bank 7) |
| Chân 139 | I/O — User I/O pin (bank 7) |
| Chân 140 | I/O — User I/O pin (bank 7) |
| Chân 141 | I/O — User I/O pin (bank 7) |
| Chân 142 | I/O — User I/O pin (bank 7) |
| Chân 143 | VCCIO7 — I/O supply voltage bank 7 (3.3V or 5V) |
| Chân 144 | I/O — User I/O pin (bank 7) |
| Chân 145 | I/O — User I/O pin (bank 7) |
| Chân 146 | I/O — User I/O pin (bank 7) |
| Chân 147 | I/O — User I/O pin (bank 7) |
| Chân 148 | I/O — User I/O pin (bank 7) |
| Chân 149 | I/O — User I/O pin (bank 7) |
| Chân 150 | I/O — User I/O pin (bank 7) |
| Chân 151 | I/O — User I/O pin (bank 7) |
| Chân 152 | I/O — User I/O pin (bank 7) |
| Chân 153 | GND — Ground |
| Chân 154 | I/O — User I/O pin (bank 8) |
| Chân 155 | I/O — User I/O pin (bank 8) |
| Chân 156 | I/O — User I/O pin (bank 8) |
| Chân 157 | I/O — User I/O pin (bank 8) |
| Chân 158 | I/O — User I/O pin (bank 8) |
| Chân 159 | I/O — User I/O pin (bank 8) |
| Chân 160 | I/O — User I/O pin (bank 8) |
| Chân 161 | I/O — User I/O pin (bank 8) |
| Chân 162 | I/O — User I/O pin (bank 8) |
| Chân 163 | I/O — User I/O pin (bank 8) |
| Chân 164 | I/O — User I/O pin (bank 8) |
| Chân 165 | VCCINT — Internal logic supply voltage (5.0V) |
| Chân 166 | I/O — User I/O pin (bank 8) |
| Chân 167 | I/O — User I/O pin (bank 8) |
| Chân 168 | I/O — User I/O pin (bank 8) |
| Chân 169 | I/O — User I/O pin (bank 8) |
| Chân 170 | I/O — User I/O pin (bank 8) |
| Chân 171 | I/O — User I/O pin (bank 8) |
| Chân 172 | I/O — User I/O pin (bank 8) |
| Chân 173 | I/O — User I/O pin (bank 8) |
| Chân 174 | I/O — User I/O pin (bank 8) |
| Chân 175 | GND — Ground |
| Chân 176 | INPUT/GCLK1 — Global clock input 1 (dedicated) |
| Chân 177 | INPUT/OE1 — Global output enable input 1 (dedicated) |
| Chân 178 | INPUT/GCLRn — Global clear input (dedicated, active low) |
| Chân 179 | TDI — JTAG Test Data In |
| Chân 180 | TMS — JTAG Test Mode Select |
| Chân 181 | TCK — JTAG Test Clock |
| Chân 182 | NC — Not connected (per datasheet) |
| Chân 183 | VCCINT — Internal logic supply voltage (5.0V) |
| Chân 184 | NC — Not connected (per datasheet) |
| Chân 185 | TDO — JTAG Test Data Out |
| Chân 186 | NC — Not connected (per datasheet) |
| Chân 187 | INPUT/OE2 — Global output enable input 2 (dedicated) |
| Chân 188 | INPUT/GCLK2 — Global clock input 2 (dedicated) |
| Chân 189 | I/O — User I/O pin (bank 8) |
| Chân 190 | I/O — User I/O pin (bank 8) |
| Chân 191 | I/O — User I/O pin (bank 8) |
| Chân 192 | I/O — User I/O pin (bank 8) |
| Chân 193 | I/O — User I/O pin (bank 8) |
| Chân 194 | I/O — User I/O pin (bank 8) |
| Chân 195 | I/O — User I/O pin (bank 8) |
| Chân 196 | I/O — User I/O pin (bank 8) |
| Chân 197 | GND — Ground |
| Chân 198 | I/O — User I/O pin (bank 8) |
| Chân 199 | I/O — User I/O pin (bank 8) |
| Chân 200 | I/O — User I/O pin (bank 8) |
| Chân 201 | I/O — User I/O pin (bank 8) |
| Chân 202 | I/O — User I/O pin (bank 8) |
| Chân 203 | I/O — User I/O pin (bank 8) |
| Chân 204 | I/O — User I/O pin (bank 8) |
| Chân 205 | I/O — User I/O pin (bank 8) |
| Chân 206 | I/O — User I/O pin (bank 8) |
| Chân 207 | I/O — User I/O pin (bank 8) |
| Chân 208 | I/O — User I/O pin (bank 8) |
Ứng dụng tiêu biểu
EPM9560RC208-19 phù hợp cho 6 Áp dụngs: Microprocessor Bus Interface and Glue Logic, State Machine and Control Logic Replacement, Peripheral Control and I/O Expansion, Legacy System Maintenance and Aftermarket, Industrial Automation and Process Control, Telecommunications Backplane and Protocol Bridging.
Microprocessor Bus Interface and Glue Logic
The EPM9560RC208-19's 149 user I/O pins and 560 macrocells make it ideal for microprocessor bus interfacing, address decoding, and chip-select generation in 32-bit and 64-bit systems. Its 19 ns tPD comfortably supports ISA bus timing (8 MHz) and most PCI applications up to 33 MHz when used for decode-only paths. The deterministic PIA routing guarantees consistent timing regardless of logic placement, eliminating the timing closure iterations common with FPGAs.
Được đề xuất
State Machine and Control Logic Replacement
With 772 flip-flops and 560 macrocells, the EPM9560RC208-19 can consolidate dozens of discrete 74-series logic ICs into a single device, simplifying PCB layout and reducing BOM cost. The 19 ns propagation delay supports state-machine clock rates up to approximately 50 MHz, suitable for industrial control sequencers, peripheral controllers, and protocol bridges. The EEPROM-based configuration means instant-on behavior with no boot loader required.
Được đề xuất
Peripheral Control and I/O Expansion
The wide 149-I/O count of the EPM9560RC208-19 in the 208-pin RQFP package is well-suited for I/O expansion in embedded systems where a microcontroller lacks sufficient pins. Designers can implement custom peripheral interfaces such as LCD controllers, key-scan matrices, and parallel-port extenders. The 3.3-V/5-V tolerant I/O enables interfacing with mixed-voltage subsystems without external level shifters.
Được đề xuất
Legacy System Maintenance and Aftermarket
The EPM9560RC208-19 is widely used in legacy industrial, telecommunications, and military systems where PCB redesign is not feasible. Its deterministic timing and proven EEPROM-based reliability make it a trusted component for sustaining field-deployed equipment. Sourcing from authorized distributors and verified brokers is essential due to the part's obsolete lifecycle status.
Được đề xuất
Industrial Automation and Process Control
In industrial automation systems, the EPM9560RC208-19 provides reliable, deterministic logic for PLC I/O modules, motor-control interfaces, and sensor-signal conditioning. Its CMOS EEPROM technology offers excellent noise immunity and stable operation across industrial temperature ranges when ordered with the appropriate -N or -C temperature grade suffix. The JTAG ISP interface enables in-field firmware updates for deployed automation equipment.
Được đề xuất
Telecommunications Backplane and Protocol Bridging
Telecommunications backplanes benefit from the EPM9560RC208-19's deterministic 19 ns timing for protocol bridging between legacy buses such as VME, ISA, and proprietary interfaces. The 149 user I/O pins accommodate wide parallel data paths and control signals. The JTAG ISP enables remote provisioning and field upgrades, valuable for telecom infrastructure with long deployment lifetimes.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
EPM9560RC208-15
Altera Được sử dụng trong: Microprocessor Bus Interface and Glue Logic, Telecommunications Backplane and Protocol Bridging
EPM7256SRC208-10
Intel Được sử dụng trong: Microprocessor Bus Interface and Glue Logic
EPM9560RC208-17
Altera Được sử dụng trong: State Machine and Control Logic Replacement
EPM9480RC208-15
Intel Được sử dụng trong: State Machine and Control Logic Replacement
EPM9560ARI208-10
Intel Được sử dụng trong: Peripheral Control and I/O Expansion
EPM7256SQC208-10
Intel Được sử dụng trong: Peripheral Control and I/O Expansion, Peripheral Control and I/O Expansion
EPM9560RC208-15N
Intel Được sử dụng trong: Legacy System Maintenance and Aftermarket
EPM9560RC208-20C
Altera Được sử dụng trong: Legacy System Maintenance and Aftermarket
EPM9560ARI240-10N
Intel Được sử dụng trong: Industrial Automation and Process Control
EPM9560ARI208-10N
Altera Được sử dụng trong: Industrial Automation and Process Control
EPM9480RC208-20
Intel Được sử dụng trong: Telecommunications Backplane and Protocol Bridging
What is the propagation delay of the EPM9560RC208-19?
The EPM9560RC208-19 has a pin-to-pin propagation delay (tPD) of 19 ns as indicated by the -19 speed grade suffix. According to Altera MAX 9000 datasheet documentation, this timing is deterministic across all paths because the device uses a Programmable Interconnect Array (PIA) that provides uniform routing delays independent of signal placement.
How many macrocells does the EPM9560RC208-19 have?
The EPM9560RC208-19 contains 560 macrocells and 772 flip-flops within its MAX 9000 architecture. Each macrocell combines a programmable AND/OR array with a configurable flip-flop, giving the device approximately 12,000 usable gates for glue-logic integration.
Does the EPM9560RC208-19 support in-system programming via JTAG?
Yes, the EPM9560RC208-19 supports 5.0-V in-system programmability through its built-in IEEE Std. 1149.1 JTAG interface. This allows boundary-scan testing, on-board programming, and design iteration without removing the device from the PCB, simplifying prototyping and field upgrades.
What is the difference between EPM9560RC208-19 and EPM9560RC208-20?
The EPM9560RC208-19 has a 19 ns propagation delay (tPD), while the EPM9560RC208-20 has a slower 20 ns tPD. Both share the same MAX 9000 architecture, 560 macrocells, 12,000 gates, and 208-pin RQFP package, making the -19 the higher-speed, premium-priced bin.
Is the EPM9560RC208-19 still in production?
The EPM9560RC208-19 is classified as obsolete. Altera (now part of Intel) has discontinued the MAX 9000 family, and remaining inventory is sourced from authorized distributors or the secondary market. Engineers designing new products should consider MAX II, MAX V, or MAX 10 CPLD families as modern equivalents.
Where can I buy the EPM9560RC208-19 online?
The EPM9560RC208-19 is available through authorized Altera/Intel distributors and secondary-market brokers. Distributors historically carrying this part include DigiKey, Mouser, and Avnet, though stock is limited due to its obsolete lifecycle status as of 2026-09-13.
What is the price of the EPM9560RC208-19?
The EPM9560RC208-19 unit price at quantity 1 is approximately $28.50 as of 2026-09-13, based on distributor listings for remaining stock. Pricing varies with quantity break, demand, and lot date code; obsolete parts typically command premium pricing in the secondary market.
What is the lead time for EPM9560RC208-19 orders?
Lead time for the obsolete EPM9560RC208-19 typically ranges from stock to 8-12 weeks depending on the supplier. Authorized distributors may quote 6-10 weeks from factory allocation, while brokers can often ship from immediate inventory at higher unit prices.
EPM9560RC208-19 vs EPM9560ARC240-10 - which is better for new designs?
For new designs the EPM9560ARC240-10 is generally the better choice because it uses the same MAX 9000 die but in a 240-pin RQFP package and -10 speed grade, providing additional I/O and faster timing. However, if your PCB footprint is locked to the 208-pin RQFP, the EPM9560RC208-19 is the only pin-compatible option within the same speed-grading range.
When should I choose EPM9560RC208-19 over a newer CPLD like MAX V?
Choose the EPM9560RC208-19 only when maintaining compatibility with an existing 208-pin RQFP PCB layout is mandatory, or when matching legacy timing characteristics is critical. For new designs, the MAX V family (5M240ZE64, 5M570ZE100, etc.) offers lower power, smaller packages, and active lifecycle support.
What is the best drop-in replacement for EPM9560RC208-19?
The best drop-in replacement for the EPM9560RC208-19 is the EPM9560RC208-15, which shares the same 208-pin RQFP package, 560 macrocells, and MAX 9000 die with a faster 15 ns tPD. Other in-family options include the EPM9560RC208-17 and EPM9560RC208-18 for different speed-grade trade-offs.
Can the EPM9480RC208-15 replace the EPM9560RC208-19?
The EPM9480RC208-15 cannot fully drop-in replace the EPM9560RC208-19 because the EPM9480 has 480 macrocells versus 560 in the EPM9560, a 14% reduction in logic capacity. However, both share the 208-pin RQFP package, so if your design uses fewer than 480 macrocells the EPM9480RC208-15 is pin-compatible at a smaller logic capacity.
Where to download EPM9560RC208-19 datasheet PDF?
The EPM9560RC208-19 datasheet can be downloaded from the Altera MAX 9000 device family datasheet, available through the Alldatasheet archive at the URL listed in our data sources, and from Intel's PSG (Programmable Solutions Group) legacy documentation portal. The MAX 9000 datasheet typically runs approximately 182 pages covering all package and speed-grade variants.
Where to find the EPM9560RC208-19 pinout?
The EPM9560RC208-19 pinout is documented in the MAX 9000 device family datasheet. The 208-pin RQFP package assigns JTAG pins (TCK, TMS, TDI, TDO), dedicated inputs (INPUT/GCLK, INPUT/OE), power pins (VCCINT, VCCIO), and 149 user I/O pins numbered per the standard PQFP pinout convention.
What are the key specifications of EPM9560RC208-19 that engineers should know?
The EPM9560RC208-19 key specifications are: 560 macrocells, 12,000 usable gates, 772 flip-flops, 149 user I/O pins, 19 ns pin-to-pin tPD, 5.0-V VCCINT, 3.3-V/5-V tolerant I/O, IEEE 1149.1 JTAG ISP, and 208-pin RQFP package. These parameters define its place in the MAX 9000 family and govern timing, logic capacity, and board-level integration.
What is the best Intel (Altera) equivalent for the EPM9560RC208-19?
Within Intel/Altera's portfolio, the closest modern equivalents to the EPM9560RC208-19 are MAX V CPLDs such as 5M240ZE64C5N or 5M570ZE100C5N, but these are not pin-compatible because they use TQFP-64 or EQFP-100 packages rather than RQFP-208. For a true Intel/Altera pin-compatible drop-in, choose EPM9560RC208-15 or EPM9560RC208-17 from the same MAX 9000 family.
Dữ liệu tham khảo kỹ thuật cho EPM9560RC208-19 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
Choose the EPM9560RC208-19 when you need a 19 ns tPD, 560-macrocell MAX 9000 CPLD in the 208-pin RQFP package and your design timing budget accommodates the 19 ns propagation delay. Choose the EPM9560RC208-15 if you need a faster 15 ns tPD in the same package. Choose the EPM9560RC208-20 if your timing budget allows 20 ns and you want easier sourcing of the slower speed grade. For designs exceeding 480 macrocells, stay within the EPM9560 family; for smaller designs, consider the EPM9480 or EPM9400 families. For new designs, evaluate MAX V or MAX 10 CPLDs as modern, active-lifecycle alternatives with smaller packages and lower power.
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM9560RC208-15 | EPM9560RC208-17 | EPM9560RC208-18 | EPM9560RC208-20 | EPM9560RC208-20C | EPM9560RC208-15N | EPM9560RC208-15C |
|---|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | RQFP-208 | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same |
| Propagation Delay (tPD) | 19 ns | 15 ns (-21%) | 17 ns (-11%) | 18 ns (-5%) | 20 ns (+5%) | 20 ns (+5%) | 15 ns (-21%) | 15 ns (-21%) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Flip-Flops | 772 | 772 | 772 | 772 | 772 | 772 | 772 | 772 |
| User I/O | 149 | 149 | 149 | 149 | 149 | 149 | 149 | 149 |
Bảo phân biệt quan trọng
- Balanced speed-grade positioning within the MAX 9000 family (vsEPM9560RC208-15)
- Same RQFP-208 footprint enables direct substitution (vsEPM9560ARC240-10)
- Wide I/O count of 149 pins for system integration (vsEPM9480RC208-15)
Ghi chú thiết kế
Estimated: at 100 MHz toggle activity on 50% of I/O pins, the EPM9560RC208-19 draws approximately 200-400 mA from VCCINT (5.0 V). Provide at least four 0.1 uF ceramic decoupling capacitors placed adjacent to each VCCINT pin and bulk capacitance on each VCCIO bank. The eight I/O banks can be powered independently at 3.3 V or 5 V, but VCCINT must remain at 5.0 V ±5%.
Do not mix 3.3 V and 5 V signals on the same I/O bank when the bank is configured for 5-V operation - this can damage I/O structures through voltage stress. Ensure JTAG chain integrity by buffering TDI/TDO if multiple devices share the chain. Always issue a bulk erase before reprogramming an EEPROM-based MAX 9000 device to clear any residual configuration bits.
Route high-speed signals (clocks, JTAG) with controlled impedance and keep them short. The RQFP-208 package has lead inductance of approximately 5-7 nH; place decoupling capacitors within 100 mils of each supply pin. Provide a solid ground plane beneath the device for return-current paths and EMI suppression. Exposed-pad variants do not exist for this package - thermal dissipation is through the 208-pin leads.
Thông tin tuân thủ
RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Qualified
Không chì
Unknown
Không halogen
Unknown
Khoáng vật xung đột
Unknown
Original MAX 9000 family datasheet predates RoHS; specific RoHS compliance not confirmed in available data. Temperature-grade suffix (-N industrial, -C commercial) is the documented ordering code. AEC-Q100 not qualified - this part is not automotive-grade.
Dữ liệu được xác minh vào: 2026-09-13
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Tìm kiếm liên quan
EPM9560RC208-19
EPM9560RC208-19 datasheet
Altera EPM9560RC208-19
MAX 9000 CPLD 560 macrocells
RQFP-208 CPLD 19ns
EPM9560RC208-19 JTAG ISP
EPM9560RC208-19 vs EPM9560RC208-15
EPM9560RC208-19 drop-in replacement
EPM9560RC208-19 buy obsolete stock
what is the propagation delay of EPM9560RC208-19
EPM9560RC208-19 pinout RQFP-208
MAX 9000 glue logic CPLD 5V
Các bộ phận và thuật ngữ liên quan
Altera
Intel
EPM9560RC208-19
EPM9560RC208-15
EPM9560RC208-17
EPM9560RC208-18
EPM9560RC208-20
EPM9560RC208-20C
MAX 9000
CPLD
Complex Programmable Logic Device
macrocell
Logic Array Block (LAB)
Programmable Interconnect Array (PIA)
IEEE 1149.1 JTAG
in-system programmability (ISP)
RQFP-208
PQFP
JEDEC S-PQFP-G208
CMOS EEPROM
glue logic
bus interface
address decoding
state machine
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