DSPIC30F6013-30I/PF - 30 MIPS 16-bit DSC 132KB Flash | Microchip | TQFP-80
MPN： DSPIC30F6013-30I/PF ✗ 停產DSPIC30F6013-30I/PF 概覽
In the broader product taxonomy, the dsPIC30 family sits between 8-bit PIC microcontrollers and 32-bit ARM Cortex devices: a DSC is a microcontroller (MCU) augmented by a multiply-accumulate (MAC) DSP engine, single-cycle hardware multiply, and 40-bit accumulators, which is why DSCs are frequently called "DSP-capable MCUs". They are categorized as microcontrollers > 16-bit microcontrollers > digital signal controllers > power management & signal processing ICs. The DSPIC30F6013 explicitly targets motor control, audio processing, and sensorless BLDC/PMSM applications where deterministic interrupt latency and DSP horsepower matter more than raw MHz.
Key features include 8 channels of PWM with up to 16-bit resolution and three CPU-cycle PWM-to-PWM jitter, eight 16-bit timer/counters, two UART modules, two SPI ports, two I2C interfaces, a CAN 2.0B module, a 12-bit ADC with 16 channels at 200 ksps, a 16-channel 12-bit ADC supporting up to 200 ksps, and a 10-bit DAC output stage. The device supports 2.5 V to 5.5 V operation and offers both -40C to +125C industrial temperature range variants, packaged in TQFP-80.
Typical applications span motor control (sensorless BLDC, AC induction, switched reluctance), uninterruptible power supplies, audio decoding, automotive sensor fusion, and industrial drives. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found on any single distributor page.
直接替換替代品，適用於 DSPIC30F6013-30I/PF — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： DSPIC30F6013-30I/PF （相同外形與佔位） — 差異在於 Core Architecture, Package, ADC, I/O Pins, Operating Temperature.
DSPIC30F6013A-30I/PF
✅ 直接替換聯絡詢價
查看資料表 →DSPIC30F6013-20I/PF
✅ 直接替換聯絡詢價
查看資料表 →DSPIC30F6012-30I/PF
✅ 直接替換聯絡詢價
查看資料表 →DSPIC30F6012AT-30I/PF
✅ 直接替換聯絡詢價
查看資料表 →DSPIC30F6011T-30I/PF
✅ 直接替換聯絡詢價
查看資料表 →DSPIC30F6011AT-30I/PF
✅ 直接替換📋 參考替代品（不在目錄中）
DSPIC30F6013-30I/PF 最大額定值與電氣特性
| Core Architecture | dsPIC30 16-bit modified Harvard RISC + DSP engine |
| CPU Speed | 30 MIPS at 40 MHz |
| Program Memory (Flash) | 132 KB |
| Data RAM | 6 KB |
| Auxiliary Flash (EEPROM emulation) | 2 KB |
| 供應電壓 | 2.5 V to 5.5 V |
| 工作溫度範圍 | -40C to +85C (industrial, "I") |
| I/O Pins | 68 |
| ADC | 12-bit, 16 channels, 200 ksps |
| PWM Channels | 8 (16-bit, complementary outputs) |
| Timers | Five 16-bit timer/counters, one 32-bit (x8) |
| UART | 2 modules |
| SPI | 2 modules |
| I2C | 2 modules |
| CAN | CAN 2.0B (1 module) |
| 封裝 | TQFP-80 (PF), 14 mm x 14 mm, 1.0 mm height, 0.65 mm pitch |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
DSPIC30F6013-30I/PF 腳位配置
| 腳位 1 | MCLR — Master Clear reset input, active low; tied to VDD via pull-up during normal operation |
| 腳位 2 | AVDD — Analog supply voltage |
| 腳位 3 | AVSS — Analog ground reference |
| 腳位 4 | OSC1 — Crystal oscillator input |
| 腳位 5 | OSC2 — Crystal oscillator output |
| 腳位 6 | RP0/CN8/OC1 — Remappable I/O, change notification, PWM output 1 |
| 腳位 7 | RP1/CN9/OC2 — Remappable I/O, change notification, PWM output 2 |
| 腳位 8 | RP2/CN10/OC3 — Remappable I/O, change notification, PWM output 3 |
| 腳位 9 | RP3/CN11/OC4 — Remappable I/O, change notification, PWM output 4 |
| 腳位 10 | RP4/CN12/OC5 — Remappable I/O, change notification, PWM output 5 |
| 腳位 11 | RP5/CN13/OC6 — Remappable I/O, change notification, PWM output 6 |
| 腳位 12 | RP6/CN14/OC7 — Remappable I/O, change notification, PWM output 7 |
| 腳位 13 | RP7/CN15/OC8 — Remappable I/O, change notification, PWM output 8 |
| 腳位 14 | VDD — Digital supply voltage |
| 腳位 15 | VSS — Digital ground |
| 腳位 16 | RP8/U1TX — Remappable I/O / UART1 transmit |
| 腳位 17 | RP9/U1RX — Remappable I/O / UART1 receive |
| 腳位 18 | RP10/SDO1 — Remappable I/O / SPI1 data out |
| 腳位 19 | RP11/SDI1 — Remappable I/O / SPI1 data in |
| 腳位 20 | RP12/SCK1 — Remappable I/O / SPI1 clock |
| 腳位 21 | RP13/SS1 — Remappable I/O / SPI1 slave select |
| 腳位 22 | RP14/C1TX — Remappable I/O / CAN1 transmit |
| 腳位 23 | RP15/C1RX — Remappable I/O / CAN1 receive |
| 腳位 24 | RP16/SDO2 — Remappable I/O / SPI2 data out |
| 腳位 25 | RP17/SDI2 — Remappable I/O / SPI2 data in |
| 腳位 26 | RP18/SCK2 — Remappable I/O / SPI2 clock |
| 腳位 27 | RP19/SS2 — Remappable I/O / SPI2 slave select |
| 腳位 28 | RP20/SDA1 — Remappable I/O / I2C1 data |
| 腳位 29 | RP21/SCL1 — Remappable I/O / I2C1 clock |
| 腳位 30 | VDD — Digital supply voltage |
| 腳位 31 | VSS — Digital ground |
| 腳位 32 | RP22/SDA2 — Remappable I/O / I2C2 data |
| 腳位 33 | RP23/SCL2 — Remappable I/O / I2C2 clock |
| 腳位 34 | RP24/U2TX — Remappable I/O / UART2 transmit |
| 腳位 35 | RP25/U2RX — Remappable I/O / UART2 receive |
| 腳位 36 | RP26/PWM1H — Remappable I/O / PWM1 high output |
| 腳位 37 | RP27/PWM1L — Remappable I/O / PWM1 low output |
| 腳位 38 | RP28/PWM2H — Remappable I/O / PWM2 high output |
| 腳位 39 | RP29/PWM2L — Remappable I/O / PWM2 low output |
| 腳位 40 | VSS — Digital ground |
| 腳位 41 | TDI — JTAG test data input |
| 腳位 42 | TCK — JTAG test clock |
| 腳位 43 | TMS — JTAG test mode select |
| 腳位 44 | TDO — JTAG test data output |
| 腳位 45 | VDD — Digital supply voltage |
| 腳位 46 | AN0 — Analog input channel 0 / reference input |
| 腳位 47 | AN1 — Analog input channel 1 |
| 腳位 48 | AN2 — Analog input channel 2 |
| 腳位 49 | AN3 — Analog input channel 3 |
| 腳位 50 | AN4 — Analog input channel 4 |
| 腳位 51 | AN5 — Analog input channel 5 |
| 腳位 52 | VREF- — ADC negative reference |
| 腳位 53 | VREF+ — ADC positive reference |
| 腳位 54 | AVDD — Analog supply voltage |
| 腳位 55 | AVSS — Analog ground reference |
| 腳位 56 | AN6 — Analog input channel 6 |
| 腳位 57 | AN7 — Analog input channel 7 |
| 腳位 58 | AN8 — Analog input channel 8 |
| 腳位 59 | AN9 — Analog input channel 9 |
| 腳位 60 | AN10 — Analog input channel 10 |
| 腳位 61 | AN11 — Analog input channel 11 |
| 腳位 62 | AN12 — Analog input channel 12 |
| 腳位 63 | AN13 — Analog input channel 13 |
| 腳位 64 | AN14 — Analog input channel 14 |
| 腳位 65 | AN15 — Analog input channel 15 |
| 腳位 66 | VSS — Digital ground |
| 腳位 67 | RP30/PWM3H — Remappable I/O / PWM3 high output |
| 腳位 68 | RP31/PWM3L — Remappable I/O / PWM3 low output |
| 腳位 69 | RP32/PWM4H — Remappable I/O / PWM4 high output |
| 腳位 70 | RP33/PWM4L — Remappable I/O / PWM4 low output |
| 腳位 71 | RP34/PWM5H — Remappable I/O / PWM5 high output |
| 腳位 72 | RP35/PWM5L — Remappable I/O / PWM5 low output |
| 腳位 73 | RP36/PWM6H — Remappable I/O / PWM6 high output |
| 腳位 74 | RP37/PWM6L — Remappable I/O / PWM6 low output |
| 腳位 75 | RP38/PWM7H — Remappable I/O / PWM7 high output |
| 腳位 76 | RP39/PWM7L — Remappable I/O / PWM7 low output |
| 腳位 77 | RP40/PWM8H — Remappable I/O / PWM8 high output |
| 腳位 78 | RP41/PWM8L — Remappable I/O / PWM8 low output |
| 腳位 79 | PGED1 — ICSP/ICD programming data line |
| 腳位 80 | PGEC1 — ICSP/ICD programming clock line |
典型應用
DSPIC30F6013-30I/PF 適用於 7 應用s: Sensorless BLDC Motor Control, Audio Decoding / Voice Processing, Uninterruptible Power Supplies (UPS), Industrial Sensor Acquisition, Automotive Body & Climate Modules, Switched-Mode Power Supplies (SMPS), Consumer Audio Effects & Equalization.
Sensorless BLDC Motor Control
The DSPIC30F6013-30I/PF's 30 MIPS DSP engine, 8 PWM channels with 16-bit resolution and three CPU-cycle jitter, plus its 12-bit 200 ksps ADC make it ideal for sensorless BLDC/PMSM motor control. Real-time FOC algorithms require deterministic execution and synchronized ADC triggers, both of which this part supports. The 132 KB Flash fits field-oriented control firmware plus application state machines and CAN diagnostics. Use the DSPIC30F6013 where 4 PWM channels and 10 MIPS are insufficient.
推薦
Audio Decoding / Voice Processing
The DSP engine's single-cycle MAC unit, 40-bit accumulators, and dual 16-bit data paths make the DSPIC30F6013-30I/PF suitable for compressed-audio decode, voice-band codecs, and small-vocabulary speech recognition. At 30 MIPS, it can comfortably decode ADPCM, G.711, or proprietary speech codecs while still running housekeeping tasks on its MCU core. The 6 KB RAM is sufficient for ring-buffer audio frames without external memory.
推薦
Uninterruptible Power Supplies (UPS)
The DSPIC30F6013-30I/PF's high-speed ADC, PWM generators, and DSP capability make it well suited to digital control of UPS inverters, where it runs repetitive control loops on voltage and current feedback. Tight ADC-to-PWM timing ensures low distortion and stable output regulation. The 132 KB Flash accommodates control law and waveform generation tables for full-bridge inverter stages.
推薦
Industrial Sensor Acquisition
The DSPIC30F6013-30I/PF combines CAN 2.0B, dual UART, dual SPI, and dual I2C for industrial sensor hubs and process I/O aggregators. Its 200 ksps ADC samples 4-20 mA loops and bridge sensor outputs; its DSP engine performs temperature compensation and linearization in firmware. Operating from 2.5 V to 5.5 V, it pairs well with both 3.3 V and 5 V sensors commonly found on industrial interfaces.
推薦
Automotive Body & Climate Modules
The DSPIC30F6013-30I/PF's CAN 2.0B interface, multiple PWM channels, and robust -40C to +85C industrial range make it useful for non-safety automotive body electronics such as climate control panels and seat modules. The 30 MIPS core handles CAN stacks and PWM fan/PWM motor control loops in a single device. For under-hood applications needing +125C, upgrade to AEC-Q100-qualified dsPIC33 variants.
推薦
Switched-Mode Power Supplies (SMPS)
Digital control of SMPS converters benefits from the DSPIC30F6013-30I/PF's fast ADC, hardware PWM, and DSP MAC capability used for PID calculations and digital filtering on sampled current. The 132 KB Flash permits concurrent firmware updating on multiple power-stage firmware variants. The on-chip auxiliary Flash (2 KB) supports runtime tunable calibration data without external EEPROM.
推薦
Consumer Audio Effects & Equalization
Beyond basic decoding, the DSP engine inside the DSPIC30F6013-30I/PF enables real-time parametric EQ, 3D-sound processing, and active-crossover calculations in higher-end consumer audio. The MAC unit executes biquad filters and matrix mixing at low overhead. Software flexibility avoids dedicated DSP ICs and keeps the BOM short.
推薦
推薦產品摘要
工程參考資料，適用於 DSPIC30F6013-30I/PF — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | DSPIC30F6013A-30I/PF | DSPIC30F6013-20I/PF | DSPIC30F6012-30I/PF | DSPIC30F6012AT-30I/PF | DSPIC30F6011T-30I/PF |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | TQFP-80 (PF) | TQFP-80 (PF) - same | TQFP-80 (PF) - same | TQFP-80 (PF) - same | TQFP-80 (PF) - same | TQFP-80 (PF) - same |
| MIPS | 30 MIPS at 40 MHz | 30 MIPS at 40 MHz | 20 MIPS at 30 MHz | 30 MIPS at 40 MHz | 30 MIPS at 40 MHz | 30 MIPS at 40 MHz |
| Flash Memory | 132 KB | 132 KB | 132 KB | 48 KB | 48 KB | 132 KB (6011 family variant) |
| Data RAM | 6 KB | 6 KB | 6 KB | 8 KB | 8 KB | 6 KB |
| PWM Channels | 8 (16-bit) | 8 (16-bit) | 8 (16-bit) | 8 (16-bit) | 8 (16-bit) | 8 (16-bit) |
| ADC | 12-bit, 16-ch, 200 ksps | 12-bit, 16-ch, 200 ksps | 12-bit, 16-ch, 200 ksps | 12-bit, 16-ch, 200 ksps | 12-bit, 16-ch, 200 ksps | 12-bit, 16-ch, 200 ksps |
| CAN | 1 (CAN 2.0B) | 1 (CAN 2.0B) | 1 (CAN 2.0B) | 1 (CAN 2.0B) | 1 (CAN 2.0B) | 1 (CAN 2.0B) |
| Lifecycle Status | NRND | NRND / active variant | NRND | NRND | NRND | NRND |
主要差異化特點
- Pin-compatible upgrade path with silicon-revision "A" drop-in (對比DSPIC30F6013A-30I/PF)
- Same package, lower MIPS option for power-sensitive variants (對比DSPIC30F6013-20I/PF)
- Same family with expanded memory (對比DSPIC30F6012-30I/PF)
設計說明
Estimated: at 5.0 V VDD, 40 MHz operation, and full peripheral set, the DSPIC30F6013-30I/PF draws roughly 70 mA core current (~350 mW). Add an external LDO such as the MCP1727 with a 10 uF decoupling capacitor near each VDD pin; place bulk + bypass caps within 5 mm of the package. The part's AVDD can be sourced from the same rail as VDD provided AVDD is RF-decoupled from VDD with a ferrite bead for ADC noise isolation.
Estimated: at typical 3.3 V VDD / 40 MHz operation the part dissipates roughly 220 mW. For TQFP-80 (PF) package the theta_JA is ~50 C/W on a standard 2 oz 4-layer JEDEC PCB. Junction rise = (220 mW) * (50 C/W) = 11 C above ambient, comfortably below the 85 C ceiling; no heatsink is required in industrial environments. For +85 C deployments, keep ambient below 74 C to leave headroom.
Place the 8 MHz or 10 MHz crystal within 10 mm of OSC1/OSC2, keep its trace short, and guard it with a GND ring. Route PWM outputs in matched-length pairs to the gate-driver inputs to keep dead-time balanced. The MCLR line must have a 10 kohm pull-up to VDD; do not rely on internal weak pull-up alone for production boards. Reference Microchip's dsPIC30F6011/6012/6013/6014 datasheet for full PCB layout recommendations.
Watch out for the AVSS/AVDD pin placement on TQFP-80 (PF): some PCB layouts mistakenly connect AVSS to digital ground only, which introduces ADC offset error; tie AVSS directly to the analog ground plane with a star connection. The auxiliary Flash is NOT user-replaceable EEPROM - wear-out of 2 KB auxiliary Flash can limit erase/write cycles; budget for external EEPROM like MCP24AA512 if intensive logging is needed.
合規資訊
RoHS and REACH compliant per Microchip environmental statements; lead-free matte-tin terminations. The standard "-30I/PF" is not AEC-Q100 qualified; for automotive, look to AEC-Q100 grade dsPIC33 variants.
