IPG20N04S4L07ATMA1 - 40V 20A Dual N-Ch MOSFET 7.2mΩ | Infineon
MPN： IPG20N04S4L07ATMA1 ✓ 啟用中IPG20N04S4L07ATMA1 概覽
A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) array combines two independent MOSFET die in a single thermally-coupled package, allowing designers to replace two discrete DPAK parts with one smaller footprint and lower parasitics. The IPG20N04S4L07ATMA1 belongs to Infineon's OptiMOS™ T2 family and is part of the broader discrete semiconductor > MOSFET product hierarchy, bridging discrete transistors and integrated power stages used in modern power management designs.
Key features include logic-level drive (full enhancement at VGS = 4.5V), 100% avalanche-tested dice, MSL1 moisture sensitivity (peak reflow 260°C), and RoHS-compliant lead-free terminations. The exposed-drain pad of the TDSON-8-4 package provides a low thermal resistance path, enabling sustained high-current switching without external heat sinking in well-designed PCBs. Both MOSFETs share the same die family, ensuring matched R_DS(on) and switching characteristics for synchronous or half-bridge topologies.
Typical applications include automotive 12V/24V load switching, body electronics modules, ECU power distribution, electric power steering (EPS), and motor driver half-bridges. Its dual-channel configuration makes it equally suitable for synchronous buck converters where two low-side/high-side FETs share a compact footprint, and for reverse-polarity protection circuits where both polarities must be blocked.
When designing with this part, pay close attention to gate-drive voltage headroom and use a dedicated gate resistor to dampen ringing. The TDSON-8-4 footprint allows direct replacement of two DPAK footprints, enabling significant PCB area savings. Always consult the manufacturer datasheet for absolute maximum ratings and safe operating area curves before finalizing thermal design.
直接替換替代品，適用於 IPG20N04S4L07ATMA1 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： IPG20N04S4L07ATMA1 （相同外形與佔位） — 差異在於 Package, MSL Level, FET Type, Operating Temperature Range, RoHS Status.
IPG20N04S4L07AATMA1
✅ 直接替換📋 參考替代品（不在目錄中）
IPG20N04S4L-07
✅ 直接替換📋 參考替代品（不在目錄中）
IPG20N04S4L-07A
✅ 直接替換📋 參考替代品（不在目錄中）
BSC018N04LSGATMA1
✅ 直接替換聯絡詢價
查看資料表 →BSC014N04LSATMA1
✅ 直接替換聯絡詢價
查看資料表 →IPG20N04S4L07ATMA1 最大額定值與電氣特性
| Manufacturer | Infineon Technologies |
| Series | OptiMOS™ T2 |
| FET Type | 2x N-Channel (Dual, Independent) |
| Drain-to-Source Voltage (VDS) | 40 V |
| Continuous Drain Current (ID) | 20 A |
| RDS(on) Max @ VGS=10V | 7.2 mΩ (typical) |
| Power Dissipation (PD) Max | 65 W |
| 工作接面溫度 | -55°C to +175°C |
| 封裝 | PG-TDSON-8-4 (TDSON-8-4) |
| 安裝類型 | Surface Mount |
| Logic-Level Gate Drive | Yes (4.5V VGS fully enhanced) |
| MSL 等級 | MSL1 (per JEDEC J-STD-020, 260°C peak reflow) |
| AEC-Q101 Qualification | Qualified |
| Avalanche Tested | 100% (per datasheet) |
| RoHS / Lead-Free | RoHS compliant, lead-free terminations |
IPG20N04S4L07ATMA1 腳位配置
| 腳位 1 | G1 — Gate of MOSFET 1 |
| 腳位 2 | S1 — Source of MOSFET 1 |
| 腳位 3 | D1 — Drain of MOSFET 1 |
| 腳位 4 | D1 — Drain of MOSFET 1 (thermal pad tab) |
| 腳位 5 | D2 — Drain of MOSFET 2 |
| 腳位 6 | D2 — Drain of MOSFET 2 (thermal pad tab) |
| 腳位 7 | S2 — Source of MOSFET 2 |
| 腳位 8 | G2 — Gate of MOSFET 2 |
安全工作區 - DC Continuous
典型應用
IPG20N04S4L07ATMA1 適用於 6 應用s: Automotive 12V Load Switching, Electric Power Steering (EPS) Half-Bridge, Synchronous Buck Converter Power Stage, H-Bridge DC Motor Driver, Reverse-Polarity and Battery Disconnect Protection, Industrial 24V Solenoid and Valve Driver.
Automotive 12V Load Switching
The IPG20N04S4L07ATMA1 is purpose-built for 12V automotive body-electronics load switching, where its 40V VDS rating easily absorbs 35V load-dump transients and its 20A continuous current handles high inrush loads such as LED headlamp drivers, seat heaters, and power-window motors. The dual-channel configuration lets one IC drive two independent loads (e.g., left and right headlamp relays), saving PCB area versus two discrete DPAK parts. AEC-Q101 qualification and 175°C junction temperature tolerance provide the reliability margin required under-hood and in cabin modules. Designers typically place a 10Ω gate resistor and a TVS clamp on the drain to meet ISO 7637-2 surge requirements.
推薦
Electric Power Steering (EPS) Half-Bridge
In EPS motor-drive stages, the IPG20N04S4L07ATMA1's dual N-channel configuration forms a compact half-bridge for driving the brushless DC motor's low-side and high-side switches at 20A continuous. The 7.2 mΩ R_DS(on) keeps conduction losses under 1.5W per FET at full load, allowing sustained operation without external heatsinking on a 1 in² copper pour. Logic-level 4.5V gate drive permits direct interface with 5V gate-driver ICs. AEC-Q101 and 175°C TJ ratings satisfy the ASIL-relevant functional-safety demands of steering systems, while MSL1 reflow compatibility simplifies SMT assembly on automotive production lines.
推薦
Synchronous Buck Converter Power Stage
The IPG20N04S4L07ATMA1's two independent N-channel dice serve directly as the low-side and high-side switches in a 12V-to-3.3V/5V synchronous buck converter delivering up to 20A output. With 7.2 mΩ R_DS(on), the part dissipates roughly 3W at 20A, manageable on a standard 4-layer FR4 PCB with 1 oz copper and no external heatsink. The exposed-drain pad keeps thermal resistance near 40°C/W, allowing continuous operation at 20A with junction rise under 80°C. Designers pair it with a synchronous-rectifier controller such as the IR2114SSPBF to minimize switching-node ringing and achieve >93% peak efficiency in 12V-input POL converters.
推薦
H-Bridge DC Motor Driver
Two IPG20N04S4L07ATMA1 devices wired as a full H-bridge deliver bidirectional control of brushed DC motors up to 20A continuous in automotive actuators (e.g., throttle bodies, fuel pumps, mirror adjusters). Each IC provides two dice, so two parts build a complete four-FET bridge with matched R_DS(on) for balanced switching transients. The 40V VDS margin handles back-EMF spikes from inductive loads when paired with flyback diodes or active clamping. Logic-level gate drive interfaces directly with 5V H-bridge predrivers, while AEC-Q101 qualification and 175°C TJ tolerance ensure reliability across the automotive temperature range.
推薦
Reverse-Polarity and Battery Disconnect Protection
The IPG20N04S4L07ATMA1's dual N-channel configuration implements a back-to-back blocking switch for reverse-polarity protection and low-loss battery disconnect in 12V/24V automotive ECUs. Both dice share the same 7.2 mΩ R_DS(on), giving 14 mΩ total conduction loss at 20A - far lower than Schottky-diode solutions. The 40V VDS rating easily handles 24V bus transients, and 175°C TJ capability supports under-hood mounting. Logic-level drive allows the gate to be pulled up by a microcontroller GPIO or a dedicated hot-swap controller, and the exposed pad provides adequate heat dissipation for continuous 20A disconnect/connect duty.
推薦
Industrial 24V Solenoid and Valve Driver
In industrial automation, the IPG20N04S4L07ATMA1 drives 24V solenoids, hydraulic valves, and relay coils at up to 20A per channel. Its 40V VDS provides 67% headroom over a nominal 24V rail, comfortably absorbing inductive flyback spikes from solenoid turn-off. The 7.2 mΩ R_DS(on) reduces driver-stage dissipation to roughly 2.9W at 20A, eliminating the need for bulky heatsinks in PLC output modules. Logic-level gate drive simplifies interface to 24V-to-5V logic-level shifters, and the dual-channel configuration lets one IC sink two independent solenoid loads - cutting board space by 50% versus discrete DPAK solutions.
推薦
推薦產品摘要
工程參考資料，適用於 IPG20N04S4L07ATMA1 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | IPG20N04S4L07AATMA1 | IPG20N04S4L-07 | IPG20N04S4L-07A | BSC018N04LSGATMA1 | BSC014N04LSATMA1 |
|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-TDSON-8-4 | PG-TDSON-8-10 (same family) | PG-TDSON-8-4 (same) | PG-TDSON-8-10 (same family) | PG-TDSON-8 (same family) | PG-TDSON-8 (same family) |
| VDS Max | 40 V | 40 V | 40 V | 40 V | 40 V | 40 V |
| Continuous Drain Current | 20 A (per channel) | 20 A (per channel) | 20 A (per channel) | 20 A (per channel) | Single channel, higher current | Single channel, higher current |
| RDS(on) @ 10V | 7.2 mΩ (typ) | 7.2 mΩ (typ) | 7.2 mΩ (typ) | 7.2 mΩ (typ) | 1.8 mΩ (lower) | 1.4 mΩ (lower) |
| Configuration | Dual N-channel | Dual N-channel | Dual N-channel | Dual N-channel | Single N-channel | Single N-channel |
| Logic-Level Gate Drive | Yes (4.5V VGS) | Yes | Yes | Yes | Yes | Yes |
| AEC-Q101 Qualified | Yes | Yes | Industrial grade | Yes | Yes | Yes |
| Operating Junction Temp | -55°C to +175°C | -55°C to +175°C | -55°C to +175°C | -55°C to +175°C | -55°C to +150°C typical | -55°C to +150°C typical |
主要差異化特點
- Dual N-channel MOSFETs in one TDSON-8 package (對比BSC018N04LSGATMA1 (single N-channel))
- AEC-Q101 qualified with 175°C junction temperature (對比IPG20N04S4L-07 (industrial grade))
- Logic-level 4.5V gate drive (對比Standard 10V-gate MOSFETs)
設計說明
Estimated: at VGS=10V and ID=20A per channel, conduction loss is roughly I²·RDS(on) = 400 × 0.0072 = 2.88W per FET, totaling ~5.8W for both dice. The PG-TDSON-8-4 package has a typical RθJA near 40°C/W on a 1 in² 4-layer 1 oz copper pad, giving a junction rise of ~115°C above ambient. To stay below 150°C TJ in 85°C ambient applications, limit continuous current to ~13A per channel or increase copper area to 2-3 in². Always validate with the manufacturer's SOA curves in the final design.
Place the gate-drive resistor (typically 10Ω) within 5 mm of the gate pin to dampen parasitic ringing caused by the gate-source and gate-drain capacitances (Ciss, Crss) combined with PCB trace inductance. Keep the source-return loop as short as possible - if the source pin is connected through a long trace, use a Kelvin-source connection (pin 2 / pin 7 dedicated to gate return) to avoid feedback that slows switching and increases switching losses. The exposed drain pad must be soldered to a continuous copper pour for both thermal dissipation and low-inductance drain return.
Do not exceed VGS = ±20V absolute maximum - use a gate-source Zener clamp (typically 12V) when driving from a higher-voltage gate driver or in circuits with inductive kickback on the source. Below VGS(th) of roughly 2V the FET is in cut-off; confirm your microcontroller's GPIO high-level output (typically 3.3V or 5V) exceeds the worst-case VGS(th) plus margin under all temperature and load conditions. Also note that the two dice share the same drain tab electrically only via PCB routing - they are NOT internally connected, so always verify drain-source voltage on both channels independently.
合規資訊
AEC-Q101 automotive qualification per Infineon product page. RoHS compliant and lead-free per datasheet. MSL1 to 260°C peak reflow per JEDEC J-STD-020. 100% avalanche tested.
