EPF8820ARC160-2 - FLEX 8000 FPGA, 672 LE, 120 I/O, 160-BQFP | Intel
料号： EPF8820ARC160-2 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $19.4 | $1,940.00 |
| 500 | $16.8 | $8,400.00 |
| 1,000 | $14.95 | $14,950.00 |
EPF8820ARC160-2 概述
What is a FLEX 8000 FPGA? FLEX 8000 is a legacy SRAM-based Field-Programmable Gate Array family introduced by Altera (now Intel PSG) in the mid-1990s. Hierarchically, FLEX 8000 sits between simple PLDs/CPLDs (small logic-only devices) and modern high-density SRAM FPGAs (Cyclone, MAX series): device -> FPGA -> programmable logic -> integrated circuit -> semiconductor. FPGAs contain configurable logic blocks (here, 4-LUT-based LEs grouped into LABs), programmable routing, and I/O cells; SRAM configuration makes them in-system reprogrammable but requires a configuration memory on every power-up.
Key features include 120 user I/O pins supporting 5 V TTL/CMOS interfaces, on-chip SRAM-based configuration memory, multi-volt I/O compatibility, JTAG (IEEE 1149.1) boundary-scan test support, and a 4-input Look-Up Table (LUT) logic architecture. The part is built on a 0.5 µm CMOS SRAM process (Altera FLEX 8000 family), giving it non-volatile operation only when paired with an external configuration EPROM such as the EPC1 or EPC2.
The device targets applications like industrial control glue logic, telecom line-card interface bridging, PCI bus interface bridging, custom peripherals for embedded microprocessors, and legacy replacement of 74-series and 4000-series MSI/LSI logic. With 120 I/O it can sink/source up to 25 mA per pin (typical) and supports PCI-compliant drive.
When designing with EPF8820ARC160-2, plan for configuration: a serial configuration EPROM (EPC1/EPC2) or microcontroller must load the SRAM at every power-up. The 160-BQFP package has a footprint roughly 28 mm × 28 mm; provide four-layer PCB with solid ground and power planes for noise-sensitive applications.
This page synthesizes distributor pricing, lifecycle status, and parametric comparison versus same-family Intel FLEX 8000 variants and cross-brand Xilinx XC3000/XC4000 equivalents - information that is not consolidated on any single distributor page.
直接替换替代料： EPF8820ARC160-2 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPF8820ARC160-2 （相同外形与封装尺寸） ——差异在于 Process Technology, Operating Temperature, Package, Speed Grade, Supply Voltage.
快速对比工具——选择替代料号进行并排对比：
EPF8820ARC-4N
✅ 直接替换✓ 有现货
$19.4 / 个
查看数据手册 →EPF8820ARC-4
✅ 直接替换✓ 有现货
$19.95 / 个
查看数据手册 →EPF8820ARC160-2 最大额定值与电气特性
| Series | FLEX 8000 |
| Logic Elements / Cells | 672 |
| Number of LABs / CLBs | 84 |
| Typical Gate Count | 8,000 gates |
| User I/O Pins | 120 |
| 电源电压 | 4.75 V to 5.25 V (5 V nominal) |
| 工作温度 | 0 °C to 70 °C (commercial) |
| 安装类型 | Surface Mount |
| 封装 / 外壳 | 160-BQFP (Metric Quad Flat Pack) |
| Configuration Memory | SRAM (volatile; requires external EPC1/EPC2 EPROM or MCU) |
| Process Technology | 0.5 µm CMOS SRAM |
| Logic Element Architecture | 4-input LUT + carry chain |
| Boundary Scan | JTAG IEEE 1149.1 |
| Part Status | Obsolete (per distributor listings) |
| Logic Voltage | 5 V TTL/CMOS |
EPF8820ARC160-2 引脚配置
| 引脚 1 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 2 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 3 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 4 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 5 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 6 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 7 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 8 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 9 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 10 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 11 | VCCINT — 5 V core supply |
| 引脚 12 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 13 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 14 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 15 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 16 | GND — Ground |
| 引脚 17 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 18 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 19 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 20 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 21 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 22 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 23 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 24 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 25 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 26 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 27 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 28 | VCCIO1 — I/O Bank 1 reference voltage |
| 引脚 29 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 30 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 31 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 32 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 33 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 34 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 35 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 36 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 37 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 38 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 39 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 40 | I/O Bank 1 — User I/O - Bank 1 |
| 引脚 41 | GND — Ground |
| 引脚 42 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 43 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 44 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 45 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 46 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 47 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 48 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 49 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 50 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 51 | VCCINT — 5 V core supply |
| 引脚 52 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 53 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 54 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 55 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 56 | GND — Ground |
| 引脚 57 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 58 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 59 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 60 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 61 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 62 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 63 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 64 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 65 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 66 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 67 | VCCIO2 — I/O Bank 2 reference voltage |
| 引脚 68 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 69 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 70 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 71 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 72 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 73 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 74 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 75 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 76 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 77 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 78 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 79 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 80 | I/O Bank 2 — User I/O - Bank 2 |
| 引脚 81 | GND — Ground |
| 引脚 82 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 83 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 84 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 85 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 86 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 87 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 88 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 89 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 90 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 91 | VCCINT — 5 V core supply |
| 引脚 92 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 93 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 94 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 95 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 96 | GND — Ground |
| 引脚 97 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 98 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 99 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 100 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 101 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 102 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 103 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 104 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 105 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 106 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 107 | VCCIO3 — I/O Bank 3 reference voltage |
| 引脚 108 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 109 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 110 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 111 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 112 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 113 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 114 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 115 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 116 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 117 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 118 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 119 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 120 | I/O Bank 3 — User I/O - Bank 3 |
| 引脚 121 | GND — Ground |
| 引脚 122 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 123 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 124 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 125 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 126 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 127 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 128 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 129 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 130 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 131 | VCCINT — 5 V core supply |
| 引脚 132 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 133 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 134 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 135 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 136 | GND — Ground |
| 引脚 137 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 138 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 139 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 140 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 141 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 142 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 143 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 144 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 145 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 146 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 147 | VCCIO4 — I/O Bank 4 reference voltage |
| 引脚 148 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 149 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 150 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 151 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 152 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 153 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 154 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 155 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 156 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 157 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 158 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 159 | I/O Bank 4 — User I/O - Bank 4 |
| 引脚 160 | I/O Bank 4 — User I/O - Bank 4 |
典型应用
EPF8820ARC160-2 适用于 6 应用s: Legacy Industrial Glue Logic, PCI Bus Bridge / Interface Bridging, Telecom Line-Card Interface Logic, Embedded Microcontroller Peripheral Expansion, Custom State Machines and Protocol Controllers, Legacy Replacement and Field Repair.
Legacy Industrial Glue Logic
The EPF8820ARC160-2 fits legacy industrial glue-logic applications that previously required dozens of 74-series MSI parts. Its 672 logic elements deliver roughly 8,000 usable gates, enough to integrate address decoding, bus arbitration, custom state machines, and interrupt controllers on a single 5 V device. With 120 user I/O, the part can replace a full board of discrete logic while running from the same 5 V supply as the surrounding TTL/CMOS circuitry. Engineers use the FLEX 8000 architecture to retain in-system reprogrammability during system bring-up, allowing last-minute logic fixes without board respins.
推荐
PCI Bus Bridge / Interface Bridging
The EPF8820ARC160-2 is widely used as a PCI bus bridge or interface bridging device between microprocessors, DSPs, and legacy peripherals. Its 120 user I/O pins can carry an entire 32-bit PCI bus (32 data/address + 8 control) plus ancillary control lines, and the 4-input LUT + carry-chain architecture synthesizes 32-bit counters, FIFOs, and address-decoding logic efficiently. The 5 V TTL I/O is PCI-compliant when the device is configured in PCI mode. Designers appreciate the in-system SRAM programmability for fixing protocol bugs in the field without respinning the host board.
推荐
Telecom Line-Card Interface Logic
Telecom line-card and central-office designs adopted the FLEX 8000 family for custom interface and framing logic. The EPF8820ARC160-2 with 672 LEs and 120 I/O implements HDLC controllers, framing bit-processors, T1/E1 line-interface glue, and custom serial-to-parallel converters on a single device. Its commercial 0 °C to 70 °C range suits environmentally controlled CO bays. The 160-BQFP package's large thermal copper pad area also helps dissipate heat in enclosed, fan-less line-card assemblies. JTAG boundary-scan eases in-system test of the dense BQFP footprint.
推荐
Embedded Microcontroller Peripheral Expansion
Embedded designs using 8-bit and 16-bit microcontrollers (8051, 68xxx, MIPS, x86) often lack I/O or peripheral features, and the EPF8820ARC160-2 serves as a configurable peripheral-expansion companion. With 120 I/O it adds parallel ports, PWM generators, quadrature decoders, or custom serial interfaces (UART, SPI, I2C master/slave) next to a host MCU that has run out of pins. The 5 V supply matches legacy MCU rails, and in-system SRAM programmability allows firmware engineers to update peripheral behavior alongside MCU firmware revisions.
推荐
Custom State Machines and Protocol Controllers
The EPF8820ARC160-2 is a natural fit for complex state-machine and protocol-controller implementations where discrete 74LS/74AS state machines would consume too much board area. With 672 4-input LUT-based logic elements, the device can implement multi-state machines with hundreds of states, packet-framing logic, custom synchronous protocols, and proprietary bus controllers. Engineers benefit from FPGA design tools that synthesize state machines directly from HDL descriptions, and the in-system reprogrammability allows rapid protocol iteration during OEM development.
推荐
Legacy Replacement and Field Repair
Many long-lifecycle industrial, military, and avionics systems still contain EPF8820ARC160-2 devices that must be repaired for decades. The part supports legacy replacement and field-repair workflows by enabling direct PCB-level swaps on existing 160-BQFP land patterns. Distributors Ocean-Components, Wolfchip, and Micro-Semiconductor report thousands of remaining new-old-stock pieces, which feeds the aftermarket repair pipeline. The 5 V supply, JTAG test, and known-good bitstream ensure repaired systems retain original functionality without requalification.
推荐
推荐产品汇总
工程参考数据： EPF8820ARC160-2 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPF8820AQC160-2 | EPF8820ARC-4N | EPF8820ARC-4 | EPF8820AGC192-2 | EPF8820ABC225-4 |
|---|---|---|---|---|---|---|
| Package | 160-BQFP (Metric QFP) | 160-pin PQFP (JEDEC QFP) - land pattern differs | 160-BQFP (Metric QFP) - same footprint | 160-BQFP (Metric QFP) - same footprint | 192-pin PGA - package differs | 225-BGA - package differs |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 672 | 672 | 672 | 672 | 672 | 672 |
| LABs / CLBs | 84 | 84 | 84 | 84 | 84 | 84 |
| User I/O | 120 | 120 | 120 | 120 | 120 (same die, fewer routed to package) | 120 (same die, more package pins available) |
| Speed Grade | -2 | -2 | -4 (faster) | -4 (faster) | -2 | -4 (faster) |
| Supply Voltage | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) |
| Operating Temperature | 0 to 70 °C | 0 to 70 °C | 0 to 70 °C | 0 to 70 °C | 0 to 70 °C | 0 to 70 °C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- True drop-in speed-grade upgrade on identical 160-BQFP land pattern （对比 EPF8820ARC-4N)
- Same die in higher-pin-count package enables I/O reassignment （对比 EPF8820AGC192-2)
- Lowest-cost entry point into the FLEX 8000 family with 120 I/O （对比 EPF8820ABC225-4)
设计说明
The EPF8820ARC160-2 requires a clean 5 V supply (4.75 V to 5.25 V) on VCCINT pins, plus separate VCCIO1/VCCIO2/VCCIO3/VCCIO4 rails for each of the four I/O banks. Estimated: a fully utilized EPF8820 with all 120 I/O toggling at 50 MHz draws roughly 200-300 mA on VCCINT plus I/O supply current proportional to loading. Decouple each VCC/VCCIO pin with a 0.1 µF ceramic and place a bulk 47 µF tantalum near the device. Configuration EPROM supply must ramp within Intel-specified tRSTL/VCC timing to avoid configuration failure.
The 160-BQFP (Metric Quad Flat Pack) has a 0.65 mm pitch and ~28 mm body. Provide 4-layer PCB with solid ground and power planes directly under the device for VCCINT/GND return paths. Keep configuration EPROM (EPC1/EPC2) within 50 mm to minimize passive-serial trace length. Use 0.1 µF decoupling within 5 mm of each VCC pin. JTAG chain should have a 10 kΩ pull-up on TCK/TMS/TDI to keep the boundary-scan state valid at power-up.
Common pitfalls with EPF8820ARC160-2 designs: (1) forgetting that configuration SRAM is volatile - the device WILL NOT retain its design without an external EPC1/EPC2 EPROM or MCU passive-serial master; (2) mixing 160-BQFP metric) and 160-PQFP (JEDEC) land patterns - they are NOT identical; (3) ignoring the speed-grade downgrades: replacing -4 with -2 reduces timing margin; (4) leaving JTAG chain unterminated can lock the device into a non-functional state during power-up; (5) using 3.3 V signals on a 5 V VCCIO bank without level translation violates Absolute Maximum Ratings.
合规信息
Compliance status not stated in verified web data; legacy 1990s FLEX 8000 parts typically pre-date RoHS but were offered in lead-free variants under the 'N' suffix. AEC-Q100 not applicable - this is a commercial-grade FPGA, not automotive-qualified.
