EPF8820ARC160-2 - FLEX 8000 FPGA, 672 LE, 120 I/O, 160-BQFP | Intel
MPN: EPF8820ARC160-2 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $19.4 | $1,940.00 |
| 500 | $16.8 | $8,400.00 |
| 1,000 | $14.95 | $14,950.00 |
Drop-in alternatives for EPF8820ARC160-2 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPF8820ARC-4N
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View Datasheet βEPF8820ARC160-2 Maximum Ratings & Electrical Characteristics
| Series | FLEX 8000 |
| Logic Elements / Cells | 672 |
| Number of LABs / CLBs | 84 |
| Typical Gate Count | 8,000 gates |
| User I/O Pins | 120 |
| Supply Voltage | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) |
| Mounting Type | Surface Mount |
| Package / Case | 160-BQFP (Metric Quad Flat Pack) |
| Configuration Memory | SRAM (volatile; requires external EPC1/EPC2 EPROM or MCU) |
| Process Technology | 0.5 Β΅m CMOS SRAM |
| Logic Element Architecture | 4-input LUT + carry chain |
| Boundary Scan | JTAG IEEE 1149.1 |
| Part Status | Obsolete (per distributor listings) |
| Logic Voltage | 5 V TTL/CMOS |
EPF8820ARC160-2 Pin Configuration
| Pin 1 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 2 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 3 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 4 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 5 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 6 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 7 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 8 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 9 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 10 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 11 | VCCINT β 5 V core supply |
| Pin 12 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 13 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 14 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 15 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 16 | GND β Ground |
| Pin 17 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 18 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 19 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 20 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 21 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 22 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 23 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 24 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 25 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 26 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 27 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 28 | VCCIO1 β I/O Bank 1 reference voltage |
| Pin 29 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 30 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 31 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 32 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 33 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 34 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 35 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 36 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 37 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 38 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 39 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 40 | I/O Bank 1 β User I/O - Bank 1 |
| Pin 41 | GND β Ground |
| Pin 42 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 43 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 44 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 45 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 46 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 47 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 48 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 49 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 50 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 51 | VCCINT β 5 V core supply |
| Pin 52 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 53 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 54 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 55 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 56 | GND β Ground |
| Pin 57 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 58 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 59 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 60 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 61 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 62 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 63 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 64 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 65 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 66 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 67 | VCCIO2 β I/O Bank 2 reference voltage |
| Pin 68 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 69 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 70 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 71 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 72 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 73 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 74 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 75 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 76 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 77 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 78 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 79 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 80 | I/O Bank 2 β User I/O - Bank 2 |
| Pin 81 | GND β Ground |
| Pin 82 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 83 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 84 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 85 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 86 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 87 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 88 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 89 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 90 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 91 | VCCINT β 5 V core supply |
| Pin 92 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 93 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 94 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 95 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 96 | GND β Ground |
| Pin 97 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 98 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 99 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 100 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 101 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 102 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 103 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 104 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 105 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 106 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 107 | VCCIO3 β I/O Bank 3 reference voltage |
| Pin 108 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 109 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 110 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 111 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 112 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 113 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 114 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 115 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 116 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 117 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 118 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 119 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 120 | I/O Bank 3 β User I/O - Bank 3 |
| Pin 121 | GND β Ground |
| Pin 122 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 123 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 124 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 125 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 126 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 127 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 128 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 129 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 130 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 131 | VCCINT β 5 V core supply |
| Pin 132 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 133 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 134 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 135 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 136 | GND β Ground |
| Pin 137 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 138 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 139 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 140 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 141 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 142 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 143 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 144 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 145 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 146 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 147 | VCCIO4 β I/O Bank 4 reference voltage |
| Pin 148 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 149 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 150 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 151 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 152 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 153 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 154 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 155 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 156 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 157 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 158 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 159 | I/O Bank 4 β User I/O - Bank 4 |
| Pin 160 | I/O Bank 4 β User I/O - Bank 4 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820ARC160-2 is suitable for 6 applications: Legacy Industrial Glue Logic, PCI Bus Bridge / Interface Bridging, Telecom Line-Card Interface Logic, Embedded Microcontroller Peripheral Expansion, Custom State Machines and Protocol Controllers, Legacy Replacement and Field Repair.
Legacy Industrial Glue Logic
The EPF8820ARC160-2 fits legacy industrial glue-logic applications that previously required dozens of 74-series MSI parts. Its 672 logic elements deliver roughly 8,000 usable gates, enough to integrate address decoding, bus arbitration, custom state machines, and interrupt controllers on a single 5 V device. With 120 user I/O, the part can replace a full board of discrete logic while running from the same 5 V supply as the surrounding TTL/CMOS circuitry. Engineers use the FLEX 8000 architecture to retain in-system reprogrammability during system bring-up, allowing last-minute logic fixes without board respins.
Recommended
PCI Bus Bridge / Interface Bridging
The EPF8820ARC160-2 is widely used as a PCI bus bridge or interface bridging device between microprocessors, DSPs, and legacy peripherals. Its 120 user I/O pins can carry an entire 32-bit PCI bus (32 data/address + 8 control) plus ancillary control lines, and the 4-input LUT + carry-chain architecture synthesizes 32-bit counters, FIFOs, and address-decoding logic efficiently. The 5 V TTL I/O is PCI-compliant when the device is configured in PCI mode. Designers appreciate the in-system SRAM programmability for fixing protocol bugs in the field without respinning the host board.
Recommended
Telecom Line-Card Interface Logic
Telecom line-card and central-office designs adopted the FLEX 8000 family for custom interface and framing logic. The EPF8820ARC160-2 with 672 LEs and 120 I/O implements HDLC controllers, framing bit-processors, T1/E1 line-interface glue, and custom serial-to-parallel converters on a single device. Its commercial 0 Β°C to 70 Β°C range suits environmentally controlled CO bays. The 160-BQFP package's large thermal copper pad area also helps dissipate heat in enclosed, fan-less line-card assemblies. JTAG boundary-scan eases in-system test of the dense BQFP footprint.
Recommended
Embedded Microcontroller Peripheral Expansion
Embedded designs using 8-bit and 16-bit microcontrollers (8051, 68xxx, MIPS, x86) often lack I/O or peripheral features, and the EPF8820ARC160-2 serves as a configurable peripheral-expansion companion. With 120 I/O it adds parallel ports, PWM generators, quadrature decoders, or custom serial interfaces (UART, SPI, I2C master/slave) next to a host MCU that has run out of pins. The 5 V supply matches legacy MCU rails, and in-system SRAM programmability allows firmware engineers to update peripheral behavior alongside MCU firmware revisions.
Recommended
Custom State Machines and Protocol Controllers
The EPF8820ARC160-2 is a natural fit for complex state-machine and protocol-controller implementations where discrete 74LS/74AS state machines would consume too much board area. With 672 4-input LUT-based logic elements, the device can implement multi-state machines with hundreds of states, packet-framing logic, custom synchronous protocols, and proprietary bus controllers. Engineers benefit from FPGA design tools that synthesize state machines directly from HDL descriptions, and the in-system reprogrammability allows rapid protocol iteration during OEM development.
Recommended
Legacy Replacement and Field Repair
Many long-lifecycle industrial, military, and avionics systems still contain EPF8820ARC160-2 devices that must be repaired for decades. The part supports legacy replacement and field-repair workflows by enabling direct PCB-level swaps on existing 160-BQFP land patterns. Distributors Ocean-Components, Wolfchip, and Micro-Semiconductor report thousands of remaining new-old-stock pieces, which feeds the aftermarket repair pipeline. The 5 V supply, JTAG test, and known-good bitstream ensure repaired systems retain original functionality without requalification.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820ARC160-2 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820AQC160-2 | EPF8820ARC-4N | EPF8820ARC-4 | EPF8820AGC192-2 | EPF8820ABC225-4 |
|---|---|---|---|---|---|---|
| Package | 160-BQFP (Metric QFP) | 160-pin PQFP (JEDEC QFP) - land pattern differs | 160-BQFP (Metric QFP) - same footprint | 160-BQFP (Metric QFP) - same footprint | 192-pin PGA - package differs | 225-BGA - package differs |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 672 | 672 | 672 | 672 | 672 | 672 |
| LABs / CLBs | 84 | 84 | 84 | 84 | 84 | 84 |
| User I/O | 120 | 120 | 120 | 120 | 120 (same die, fewer routed to package) | 120 (same die, more package pins available) |
| Speed Grade | -2 | -2 | -4 (faster) | -4 (faster) | -2 | -4 (faster) |
| Supply Voltage | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) |
| Operating Temperature | 0 to 70 Β°C | 0 to 70 Β°C | 0 to 70 Β°C | 0 to 70 Β°C | 0 to 70 Β°C | 0 to 70 Β°C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- True drop-in speed-grade upgrade on identical 160-BQFP land pattern (vs EPF8820ARC-4N)
- Same die in higher-pin-count package enables I/O reassignment (vs EPF8820AGC192-2)
- Lowest-cost entry point into the FLEX 8000 family with 120 I/O (vs EPF8820ABC225-4)
Design Notes
The EPF8820ARC160-2 requires a clean 5 V supply (4.75 V to 5.25 V) on VCCINT pins, plus separate VCCIO1/VCCIO2/VCCIO3/VCCIO4 rails for each of the four I/O banks. Estimated: a fully utilized EPF8820 with all 120 I/O toggling at 50 MHz draws roughly 200-300 mA on VCCINT plus I/O supply current proportional to loading. Decouple each VCC/VCCIO pin with a 0.1 Β΅F ceramic and place a bulk 47 Β΅F tantalum near the device. Configuration EPROM supply must ramp within Intel-specified tRSTL/VCC timing to avoid configuration failure.
The 160-BQFP (Metric Quad Flat Pack) has a 0.65 mm pitch and ~28 mm body. Provide 4-layer PCB with solid ground and power planes directly under the device for VCCINT/GND return paths. Keep configuration EPROM (EPC1/EPC2) within 50 mm to minimize passive-serial trace length. Use 0.1 Β΅F decoupling within 5 mm of each VCC pin. JTAG chain should have a 10 kΞ© pull-up on TCK/TMS/TDI to keep the boundary-scan state valid at power-up.
Common pitfalls with EPF8820ARC160-2 designs: (1) forgetting that configuration SRAM is volatile - the device WILL NOT retain its design without an external EPC1/EPC2 EPROM or MCU passive-serial master; (2) mixing 160-BQFP metric) and 160-PQFP (JEDEC) land patterns - they are NOT identical; (3) ignoring the speed-grade downgrades: replacing -4 with -2 reduces timing margin; (4) leaving JTAG chain unterminated can lock the device into a non-functional state during power-up; (5) using 3.3 V signals on a 5 V VCCIO bank without level translation violates Absolute Maximum Ratings.
Compliance Information
Compliance status not stated in verified web data; legacy 1990s FLEX 8000 parts typically pre-date RoHS but were offered in lead-free variants under the 'N' suffix. AEC-Q100 not applicable - this is a commercial-grade FPGA, not automotive-qualified.
