Intel

EP1K10TC144-3N - 10K Gate ACEX-1K FPGA, 144-LQFP | Altera / Intel

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2.5 V Vdss 144-LQFP (TQFP) Package -3N (enhanced) Speed

À partir de $10.5 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-06

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$18.5	$18,50
10	$16.2	$162,00
100	$13.95	$1 395,00
500	$12.1	$6 050,00
1 000	$10.5	$10 500,00

ℹ️ Tous les prix sont en USD

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EP1K10TC144-3N Présentation

The Intel (formerly Altera) EP1K10TC144-3N is a member of the ACEX-1K family of Field Programmable Gate Arrays (FPGAs) featuring 10,000 typical gates, 576 logic elements, and 12,288 RAM bits in a 144-pin LQFP (TQFP) package. It is built on a 0.22 um CMOS process with a 2.5 V core supply and supports -1 speed-grade PCI compliance at 5.0 V I/O. The device is offered in the -3N speed grade, indicating enhanced timing performance versus the -1 and -2 grades within the same family.

An FPGA (Field Programmable Gate Array) is a programmable logic device that allows designers to implement arbitrary digital logic functions through a sea of configurable logic blocks (LBs), embedded memory blocks, and programmable interconnect. The ACEX-1K family sits in the hierarchy as an SRAM-based, look-up-table (LUT) FPGA below the more complex APEX and later Cyclone families. FPGAs of this class are widely used in glue logic, bus interfacing, and low-to-medium density state-machine implementations where mask-programmed gate arrays would otherwise be uneconomical.

Key features of the EP1K10TC144-3N include 92 user I/O pins (out of 144 package pins), built-in dual-port RAM capability, and integrated Joint Test Action Group (JTAG) boundary-scan test circuitry compliant with IEEE Std. 1149.1-1990. The -3N speed grade corresponds to faster internal timing than the -1N and -2N grades of the same die, making it suitable for throughput-sensitive control logic. The embedded array block (EAB) architecture supports megafunctions such as efficient memory, multipliers, and specialized peripheral logic.

Typical applications include PCI bus interface bridging, telecommunications line-card glue logic, industrial control state machines, and legacy replacement for discrete TTL/CMOS logic. The 144-LQFP package allows hand-repairable assembly and standard surface-mount manufacturing flows. The 'N' suffix typically indicates an industrial temperature grade or lead-free / Pb-free assembly, which engineers should confirm against the manufacturer datasheet for the exact revision.

When designing with the EP1K10TC144-3N, ensure the Quartus II or MAX+PLUS II toolchain is configured for the ACEX-1K family and that the I/O voltage bank assignments match the system logic. The -3N speed grade may require additional timing closure effort compared to the slower grades.

This page synthesizes distributor availability, same-family drop-in alternatives (such as the -1N and -2N speed grades), and design considerations not consolidated in any single manufacturer document.

Alternatives de remplacement direct pour EP1K10TC144-3N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EP1K10TC144-3N (même facteur de forme et même empreinte) — différant par Package, Process Technology, Speed Grade, Configuration Method, Typical Gates.

EP1K10TC100-3N

Intel

Package: 100-pin TQFP

Process Technology: 0.22 µm CMOS

Speed Grade: -3 (commercial)