MPC875VR133 - PowerQUICC 133MHz 32-Bit MPU | NXP
Référence : MPC875VR133 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $48.5 | $48,50 |
| 10 | $42.2 | $422,00 |
| 100 | $36.8 | $3 680,00 |
| 500 | $31.4 | $15 700,00 |
| 1 000 | $27.9 | $27 900,00 |
MPC875VR133 Présentation
A microprocessor (MPU) is a single-chip CPU containing the arithmetic logic unit, control unit and register set that fetches, decodes and executes instructions from memory. Embedded MPUs such as the MPC875VR133 extend the base CPU with on-chip SRAM, interrupt controllers, timers and - in the PowerQUICC family - dedicated communications peripherals, eliminating the need for external coprocessors. Within the broader taxonomy, this part sits inside microcontrollers -> embedded processors -> 32-bit RISC microprocessors -> Power Architecture devices -> PowerQUICC communications processors.
Key differentiating features include the integrated CPM (Communications Processor Module) co-processor that offloads protocol processing from the core, dual Fast Ethernet controllers (10/100 Mbps) with MII/RMII interfaces, HDLC/SDLC, UART, I²C and SPI serial channels, and a memory controller supporting SDRAM, Flash and SRAM. A PCI bridge and PCMCIA host adapter are also integrated for legacy connectivity. According to the Freescale/NXP datasheet, the device performs 176 MIPS at 133 MHz core clock with 1.8 V internal logic and 3.3 V I/O.
Typical applications include branch-office routers, xDSL/Cable modems, low-end switches, industrial control gateways and wireline/wireless base-station controllers. In each scenario the integrated CPM removes the need for a separate network processor. Designers should plan thermal dissipation through the top-side PBGA thermal pad and verify DDR/SDRAM timing margins against the 133 MHz system bus; a buffered DIMM topology is recommended when more than one memory device is used.
Alternatives de remplacement direct pour MPC875VR133 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec MPC875VR133 (même facteur de forme et même empreinte) — différant par Manufacturer, Operating Temperature, RoHS Status, Core Architecture, Core Voltage.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
MPC875CVR133
✅ Remplacement direct✓ En stock
$43.75 / unité
Voir la fiche technique →MPC870ZT133
✅ Remplacement direct✓ En stock
$28.75 / unité
Voir la fiche technique →MPC852TCVR50A
✅ Remplacement direct✓ En stock
$22.1 / unité
Voir la fiche technique →MPC852TCZT50A
✅ Remplacement direct✓ En stock
$13.85 / unité
Voir la fiche technique →KMPC875VR133
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MPC875VR133 Valeurs maximales et caractéristiques électriques
| Manufacturer | NXP Semiconductors (formerly Freescale Semiconductor) |
| Series | PowerQUICC, MPC8xx |
| Core Architecture | Power Architecture (32-bit RISC) |
| Core Count | 1 |
| Core Frequency | 133 MHz |
| Performance | 176 MIPS |
| Largeur du bus de données | 32 bit |
| Process Technology | 0.18 µm CMOS |
| Supply Voltage (I/O) | 3.3 V |
| Température de fonctionnement | 0 °C to +95 °C |
| Package Type | 256-PBGA (HBGA), 23x23 mm |
| Terminal Pitch | 1.27 mm |
| On-chip Communications | CPM (HDLC/Sync UART/I²C/SPI), 2x 10/100 Ethernet MII/RMII |
| Memory Controller | SDRAM, Flash, SRAM, ROM support |
| PCI Bridge | Integrated (PCI 2.1) |
| Type de montage | Surface Mount (BGA) |
Configuration des broches de MPC875VR133
| Broche A1 | VDD — Core supply (1.8 V internal) |
| Broche A2 | VSS — Ground |
| Broche B1 | A0 — Address bus / GPIO |
| Broche B2 | DQ0 — Data bus bit 0 |
| Broche D5 | TX_EN1 — Ethernet 1 transmit enable |
| Broche E5 | RXD1[0] — Ethernet 1 receive data 0 |
| Broche F10 | PCI_AD0 — PCI address/data bit 0 |
| Broche F11 | PCI_FRAME — PCI frame signal |
| Broche H12 | UART1_TXD — UART1 transmit data |
| Broche J12 | UART1_RXD — UART1 receive data |
| Broche L14 | I2C_SDA — I²C serial data |
| Broche L15 | I2C_SCL — I²C serial clock |
| Broche N16 | IRQ0 — External interrupt request 0 |
| Broche P16 | RESET — Hard reset input |
| Broche T18 | TCK — JTAG test clock |
| Broche T19 | TDI — JTAG test data in |
| Broche U20 | TDO — JTAG test data out |
| Broche U21 | TMS — JTAG test mode select |
Applications typiques
MPC875VR133 convient pour 6 applications: Branch-Office Routers, xDSL and Cable Modems, Low-End Network Switches, Industrial Control Gateways, Wireline Base Station Controllers, Legacy Embedded Computing Platforms.
Branch-Office Routers
The MPC875VR133 is well-suited for small-to-medium branch-office routers because its 133 MHz Power Architecture core delivers 176 MIPS, enough to run a Linux or VxWorks routing stack with QoS, while the integrated dual 10/100 Ethernet MACs with MII/RMII directly connect to external PHYs without a switch ASIC. The on-chip CPM co-processor offloads HDLC/PPP framing from the CPU, freeing the core for routing-table lookups and packet forwarding. With a 256-PBGA (23x23 mm) footprint and 3.3 V I/O, the design drops onto a 4-layer PCB using standard SDRAM and Flash, reducing BOM cost versus a discrete CPU-plus-NPU architecture. Source: Freescale/NXP MPC875 datasheet application section.
Recommandé
xDSL and Cable Modems
In xDSL/Cable modem designs the MPC875VR133's integrated CPM co-processor runs HDLC, ATM and PPP framing at line rate without burdening the host CPU, while the 32-bit Power Architecture core handles upper-layer protocols such as PPPoE, IP and TCP/IP stacks. The 133 MHz core with 176 MIPS is sufficient for ADSL2+ downstream throughput, and the memory controller directly interfaces SDRAM and Flash for a complete SoC-like BOM. The 256-PBGA package at 23x23 mm fits the slim form factors of CPE equipment, and the 3.3 V I/O simplifies PHY and line-driver interface. Source: Freescale/NXP MPC875 hardware specifications, PowerQUICC family brief.
Recommandé
Low-End Network Switches
The MPC875VR133 is a fit for low-end managed Ethernet switches where the integrated dual 10/100 Ethernet MACs feed an external switch fabric via MII/RMII, while the 133 MHz core runs a lightweight L2 management stack (SNMP, RMON, VLAN). The PCI bridge and PCMCIA host adapter enable connection to expansion cards and management modules, eliminating the need for a separate bridge IC. With 176 MIPS of CPU headroom, the part can sustain management-plane traffic even with full line-rate forwarding handled externally. The 256-PBGA (23x23 mm) package suits compact switch mainboards with limited board area. Source: Freescale/NXP MPC875 datasheet.
Recommandé
Industrial Control Gateways
Industrial protocol gateways benefit from the MPC875VR133's mix of legacy and modern serial interfaces: UART, HDLC, I²C and SPI connect directly to fieldbus devices (Modbus, Profibus, CAN via external transceiver) while the 10/100 Ethernet MAC uplinks to plant networks. The 0-95 °C operating temperature covers most indoor industrial enclosures, and the 256-PBGA package withstands the vibration profile of cabinet-mounted equipment when paired with proper PCB staking. The CPM co-processor handles deterministic serial framing while the 133 MHz core runs the gateway application logic, suiting IEC 61131-style control translation. Source: Freescale/NXP MPC875 datasheet, PowerQUICC industrial positioning.
Recommandé
Wireline Base Station Controllers
For wireline base-station controllers, the MPC875VR133 provides the deterministic serial throughput required for E1/T1 trunking via its HDLC channels, plus an Ethernet MAC for backhaul and management. The 133 MHz core is sufficient to terminate dozens of voice channels under a soft-switch architecture, and the integrated memory controller simplifies SDRAM-based voice buffer design. The 256-PBGA package at 23x23 mm and 3.3 V I/O fit the dense backplane geometry of small BTS shelves. Source: Freescale/NXP MPC875 datasheet.
Recommandé
Legacy Embedded Computing Platforms
The MPC875VR133 is widely deployed in legacy embedded computing platforms (industrial PCs, point-of-sale terminals, medical instrumentation controllers) where its Power Architecture core, VxWorks/Linux support and integrated peripherals remain adequate. The 133 MHz clock and 176 MIPS sustain typical control workloads, while the 256-PBGA footprint is compatible with the original board layout. For sustaining these platforms, designers typically stock the MPC875VR133 or its drop-in sibling MPC875CVR133 to avoid board re-spin. Source: Freescale/NXP MPC875 family application notes.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour MPC875VR133 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | MPC875CVR133 | MPC870ZT133 | MPC852TCVR50A | MPC852TCZT50A | KMPC875VR133 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 256-PBGA (HBGA) 23x23 mm | 256-PBGA 23x23 mm - same | 256-PBGA 23x23 mm - same | 256-BGA - same family | 256-BGA - same family | 256-BGA Tray - same |
| Core Frequency | 133 MHz | 133 MHz | 133 MHz | 50 MHz | 50 MHz | 133 MHz |
| Core Architecture | Power Architecture (32-bit) | Power Architecture (32-bit) | Power Architecture (32-bit) | Power Architecture (32-bit) | Power Architecture (32-bit) | Power Architecture (32-bit) |
| Ethernet MACs | 2 (10/100 MII/RMII) | 2 (10/100) | 1 (10/100) | 1 (10/100) | 1 (10/100) | 2 (10/100) |
| Supply Voltage | 3.3 V I/O | 3.3 V I/O | 3.3 V I/O | 3.3 V I/O | 3.3 V I/O | 3.3 V I/O |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Dual 10/100 Ethernet MACs integrated (vs MPC870ZT133)
- Full PowerQUICC CPM feature set vs PowerQUICC II lite (vs MPC852TCVR50A)
- Drop-in identical-function trace equivalent (vs KMPC875VR133)
Notes de conception
The MPC875VR133 in 256-PBGA (23x23 mm) dissipates several watts under full Ethernet + CPM load; a thermal pad on the top of the package must be soldered to a copper pour and stitched with thermal vias to the internal ground plane. At 0-95 °C ambient, estimated junction rise from 1 square inch of 2 oz copper is approximately 8-12 °C/W, leaving comfortable margin. Source: Freescale MPC875 hardware specifications thermal section.
Route SDRAM traces with controlled 50 ohm single-ended impedance and length-match the byte lanes within 50 mils; the MPC875VR133 memory controller does not perform deskew. Place four 0.1 µF X7R decoupling capacitors within 5 mm of the PBGA power balls, plus a 10 µF bulk tantalum per supply domain. Keep the PCI bus traces under 1.5 inches if running at 33 MHz to stay within the 10 ns setup/hold budget. Source: Freescale MPC875 hardware specifications layout guidelines.
Power-on reset sequencing must follow the Freescale/NXP reference: drive RESET low for at least 100 µs after 3.3 V reaches 90 % of nominal, then release. ESTA (early sample) and TRST (JTAG reset) signals must be tied through proper pull resistors to avoid latch-up at boot. Use a supervisory reset IC rather than an RC network for production designs, since the CPM PLL requires a stable clock before initialization. Source: Freescale MPC875 datasheet.
Do not assume the MPC875VR133 PBGA pinout is identical to the MPC860/MPC8260 family - signal multiplexing differs across the MPC8xx series, and reusing an MPC860 netlist will produce non-functional boards. Verify all ball assignments against the latest NXP MPC875 hardware specifications before committing the PCB layout. Source: Freescale/NXP MPC875 datasheet pinout section.
Informations de conformité
Compliance data not present in the Verified Web Data; refer to NXP/Freescale product environmental compliance page or the original datasheet for confirmation.
