10AX090N3F45I2LG - Arria 10 GX 900K LE FPGA | Intel FPGA | 28nm
부품 번호: 10AX090N3F45I2LG ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $3850 | $3,850.00 |
| 10 | $3680 | $36,800.00 |
| 100 | $3450 | $345,000.00 |
| 500 | $3220 | $1,610,000.00 |
| 1,000 | $2995 | $2,995,000.00 |
10AX090N3F45I2LG 개요
A Field-Programmable Gate Array (FPGA) is a reconfigurable semiconductor that combines programmable logic fabric, hierarchical routing, dedicated DSP blocks, embedded memory, and high-speed transceiver channels on a single die. FPGAs occupy the middle ground between fixed-function ASICs and software-programmable processors: they deliver hardware-timed deterministic latency, parallel data-path execution, and post-silicon design changes without respinning a mask set. Within Intel's portfolio, the Arria 10 family targets mid-range applications that need transceivers above 10 Gbps and DSP throughput below the Stratix 10 tier.
Key features include 28.05 Gbps transceiver support, hardened floating-point DSP blocks for 1.5 TFLOPS, 24 transceivers on the GX die variant, and PCI Express Gen3 x8 hard IP. The 1932-ball FCBGA package exposes 48 transceiver lanes and 768 general-purpose I/Os organized in 12 I/O banks with support for DDR4, QDR-IV, and RLDRAM3 external memory interfaces.
The architecture pairs a fabric of adaptive logic modules (ALMs) with 2,000+ variable-precision DSP blocks and 28 Mb of on-chip RAM distributed as M20K blocks. Hard memory controllers and hard PCIe Gen3 IP reduce soft-logic overhead, letting engineers dedicate more LE resources to application code rather than infrastructure. The 20nm process allows higher logic density at lower core voltage, trading absolute maximum frequency for improved power efficiency versus 28nm predecessors.
Typical applications include 100G optical line-card MAC/PHY aggregation, radar and electronic-warfare signal processing, medical imaging pipelines, 4K video broadcast encoding, and ASIC prototyping. Industrial-grade screening makes the device viable for fan-less outdoor telecom equipment where convection cooling is the only thermal path.
When designing with this part, use the Quartus Prime design suite for synthesis, place-and-route, and timing closure. Power estimation requires the Early Power Estimator (EPE) before RTL is complete, because the 0.9V core rail can deliver hundreds of amps under peak DSP load. A multi-phase PMIC with per-rail voltage sequencing is mandatory for the core, transceiver, and auxiliary supplies.
This page synthesizes distributor pricing, parameter-by-parameter drop-in alternatives from the Arria 10 family, and practical PCB thermal guidance beyond what the manufacturer datasheet presents in isolation.
드롭인 대체품: 10AX090N3F45I2LG — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: 10AX090N3F45I2LG (동일 폼 팩터 및 풋프린트) — 차이점: Package, Speed Grade, Transceivers, Process Technology, DSP Blocks.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
10AX090N3F45E2LG
✅ 드롭인✓ 재고 있음
$2285 / 개
데이터시트 보기 →10AX090N3F40I2LG
✅ 드롭인✓ 재고 있음
$9800 / 개
데이터시트 보기 →10AX090N3F40I2SG
✅ 드롭인✓ 재고 있음
$2250 / 개
데이터시트 보기 →10AX090N3F40E2LG
✅ 드롭인✓ 재고 있음
$2280 / 개
데이터시트 보기 →10AX090N2F45I2LG
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →10AX090N2F45I2SG
✅ 드롭인✓ 재고 있음
$3475 / 개
데이터시트 보기 →10AX090N2F45E2LG
✅ 드롭인✓ 재고 있음
$6095.25 / 개
데이터시트 보기 →10AX090N3F45I2LG 최대 정격 & 전기적 특성
| Family | Arria 10 GX |
| Logic Elements | 900,000 |
| Embedded Memory (bits) | 59,234,304 |
| User I/O Count | 768 |
| Core Voltage | 0.9 V |
| Process Technology | 20 nm |
| Transceiver Data Rate (max) | 28.05 Gbps |
| Number of Transceivers | 24 |
| DSP Blocks | Variable-precision, 1.5 TFLOPS |
| 패키지 | 1932-ball FCBGA |
| 동작 온도 | -40C to +100C (Industrial) |
| 실장 유형 | Surface Mount (BGA) |
| PCIe Hard IP | Gen3 x8 |
| Memory Controller Hard IP | DDR4, QDR-IV, RLDRAM3 |
| Configuration | SRAM-based, volatile |
| RoHS 상태 | Compliant |
10AX090N3F45I2LG 핀 구성
| 핀 A1 | GND — Ground reference |
| 핀 A2 | VCC — Core supply (0.9 V) |
| 핀 B1 | IO_BANK_1A — I/O bank 1A signal |
일반적인 애플리케이션
10AX090N3F45I2LG 적합 용도: 6 애플리케이션s: 100G Optical Line-Card Aggregation, Radar and Electronic-Warfare Signal Processing, Medical Imaging Pipeline, 4K Video Broadcast Encoding, ASIC Prototyping, Wireless Baseband Processing.
100G Optical Line-Card Aggregation
The 10AX090N3F45I2LG fits 100G line-card aggregation because its 24 transceivers at 28.05 Gbps support OTU4, 100GbE, and 32G FC simultaneously. The 900K logic elements hold a full tri-mode 100G MAC plus channelized framing overhead, while 768 I/Os and 12 banks interface to external DDR4 buffers. Compared with a Stratix 10 part, it trades raw fabric speed for lower BOM cost at comparable functional density.
추천
Radar and Electronic-Warfare Signal Processing
The 10AX090N3F45I2LG's 1.5 TFLOPS variable-precision DSP throughput and 28 Gbps transceivers make it ideal for radar front-end aggregation and EW processing. A single device can implement FFT, beamforming, and pulse-compression pipelines for phased-array antennas while ingesting ADC samples over multiple JESD204B links. Industrial temperature grading supports outdoor naval and ground-mobile installations.
추천
Medical Imaging Pipeline
The 10AX090N3F45I2LG is well suited to CT, MRI, and ultrasound image reconstruction pipelines that demand deterministic latency and high DSP throughput. Its variable-precision DSP blocks accelerate FFT and back-projection kernels, while the 768 I/Os aggregate high-channel-count ADC front-ends via LVDS or JESD204B. Industrial temperature screening ensures reliability in clinical-equipment environments without forced-air cooling.
추천
4K Video Broadcast Encoding
The 10AX090N3F45I2LG supports 4K broadcast encoding and transcoding thanks to its high logic density and dedicated DSP blocks for H.264/HEVC motion estimation. Multiple 12G-SDI ingest paths require 28 Gbps transceivers, which this part provides natively. Its industrial temperature rating enables fan-less rack installations in studio environments where acoustic noise is unacceptable.
추천
ASIC Prototyping
The 10AX090N3F45I2LG is an effective ASIC prototyping vehicle because its 900K logic elements partition cleanly across multiple child designs via partial reconfiguration. Quartus Prime supports time-domain multiplexing of multiple ASIC blocks, allowing early software development before tape-out. The industrial temperature variant supports prototyping for automotive and industrial ASICs.
추천
Wireless Baseband Processing
The 10AX090N3F45I2LG handles LTE and 5G baseband processing, with its high logic density accommodating multi-channel LDPC encoders and FFT chains. The 28 Gbps transceivers interface to high-data-rate fronthaul links (eCPRI, CPRI Option 9), while DDR4 hard memory controllers feed high-bandwidth sample streams. Industrial temperature grading supports outdoor small-cell deployments.
추천
추천 제품 요약
엔지니어링 참조 데이터: 10AX090N3F45I2LG — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | 10AX090N3F45E2LG | 10AX090N3F40I2LG | 10AX090N3F40I2SG | 10AX090N3F40E2LG | 10AX090N2F45I2LG |
|---|---|---|---|---|---|---|
| Package | 1932-ball FCBGA | 1932-ball FCBGA - same | 1932-ball FCBGA - same | 1932-ball FCBGA - same | 1932-ball FCBGA - same | 1932-ball FCBGA - same |
| Brand | Intel (formerly Altera) | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Transceiver Max Data Rate | 28.05 Gbps | 28.05 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 28.05 Gbps |
| Speed Grade | N3 | N3 | N3 | N3 | N3 | N2 |
| Temperature Grade | Industrial (-40C to +100C) | Commercial (0C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +100C) | Industrial (-40C to +100C) |
| User I/O Count | 768 | 768 | 768 | 768 | 768 | 768 |
| Embedded Memory (Mb) | 59.2 | 59.2 | 59.2 | 59.2 | 59.2 | 59.2 |
주요 차별점
- Highest-density Arria 10 GX at 28 Gbps (vs 10AX066N3F40E1SG)
- Industrial temperature screening at full transceiver speed (vs 10AX090N3F45E2LG)
- N3 speed grade for highest Fmax (vs 10AX090N2F45I2LG)
설계 노트
The 1932-ball FCBGA package requires a high-performance thermal interface. Estimated: at full DSP utilization (1.5 TFLOPS) the die consumes approximately 25-35 W, which the 31x31 mm FCBGA package must dissipate through a heatsink plus thermal interface material. Junction temperature must stay below 100C for industrial-grade reliability; use the Arria 10 thermal model from Intel and de-rate by at least 15C for production margin.
Estimated: at VIN=0.9 V core and full utilization, peak core current can reach 30+ A, which mandates a multi-phase PMIC with sub-milliohm PCB distribution. Use a minimum 8-layer PCB with 2 oz copper on core planes. Sequencing must follow Intel's Power-Up Sequence: 3.3V -> 2.5V -> 1.8V -> 0.9V core within the documented ramp windows; otherwise the part may latch-up.
Use microvia or HDI PCB technology for the 1.0 mm pitch BGA escape. Escape routing through 4 vias-per-ball with via-in-pad plating is recommended for the transceiver banks. Maintain 100-ohm differential impedance for 28 Gbps SerDes lanes and 50-ohm single-ended for GPIO. Place decoupling capacitors within 100 mil of each power pin and use a 0402 footprint to keep the loop area minimal.
Do not substitute Arria 10 GX with Arria 10 GT or SX variants without re-validating the transceiver IP - the protocol hard-IP differs. Also do not use 'E2' commercial parts in industrial designs; the temperature derating will cause field failures. Always use the Quartus Prime pin-assignment file (.qsf) for the exact ordering code, since the same package can have different ball maps across temperature grades.
규정 준수 정보
RoHS and REACH compliance per Intel product page. Not AEC-Q100 qualified (industrial temperature grade, not automotive). Lead-free matte-tin finish on FCBGA balls.