10AX115N3F45I2LG - Arria 10 GX FPGA, 1.15M LEs, 1932-FCBGA | Intel
MPN: 10AX115N3F45I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9970.35 | $9,970.35 |
| 10 | $9200 | $92,000.00 |
| 50 | $8800 | $440,000.00 |
| 100 | $8450 | $845,000.00 |
| 500 | $8050 | $4,025,000.00 |
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View Datasheet →10AX115N3F45I2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 |
| User I/O Pins | 768 |
| Process Technology | 20 nm |
| Transceivers | Up to 28.05 Gbps |
| Package | 1932-BBGA, FCBGA (FC-FBGA) |
| Pin/Ball Count | 1932 |
| Speed Grade | -2 |
| Temperature Grade | Industrial (I) |
| Core Voltage | 0.9 V (typical) |
| DSP Blocks | Hardened floating-point (IEEE 754 single-precision) |
| PCI Express Hard IP | Gen3 (integrated) |
| Memory | M20K block memory + MLAB |
| Configuration | JTAG / Active Serial (AS) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AX115N3F45I2LG 1932-bbga, fcbga (fc-fbga) Pin Configuration Guide
Complete pinout information for 10AX115N3F45I2LG (1932-bbga, fcbga (fc-fbga) package) with 768 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115N3F45I2LG.
Refer to the datasheet for full pin configuration.
Estimated pin count: 768 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115N3F45I2LG is suitable for 7 applications: 5G Baseband and Fronthaul Processing, Software Defined Radio (SDR), High-Performance Digital Signal Processing, High-Speed Serial Protocol Bridging, Video Processing and Broadcast Pipelines, Test and Measurement Instrumentation, Aerospace and Defense Data Acquisition.
5G Baseband and Fronthaul Processing
The 10AX115N3F45I2LG fits 5G baseband and fronthaul processing because its 1,150,000 logic elements and hardened floating-point DSP blocks deliver the throughput needed for physical-layer (PHY) baseband, channel coding, and beamforming calculations. According to the Intel Arria 10 datasheet, the transceiver channels support up to 28.05 Gbps with native CPRI, eCPRI, and JESD204B/C protocol IP, enabling direct fronthaul links between a baseband unit and remote radio heads. Designers place the FPGA between the radio converter and the baseband ASIC, using the M20K block memory for HARQ retransmission buffers. The industrial temperature grade ensures operation in outdoor cell-site cabinets.
Recommended
Software Defined Radio (SDR)
The 10AX115N3F45I2LG suits SDR platforms because the high logic density enables wideband DDC/DUC, channelization, and multi-protocol demodulation in a single device. The hardened floating-point DSP blocks (IEEE 754 single-precision) accelerate FFT, channel estimation, and MIMO processing without burning soft logic, while the 28.05 Gbps transceivers aggregate multiple RF data converters. According to Intel Arria 10 documentation, the device's 0.9V core process delivers a favorable power-per-mFLOP profile for tactical and laboratory SDR enclosures. Industrial temperature grade supports airborne and maritime SDR deployments.
Recommended
High-Performance Digital Signal Processing
The 10AX115N3F45I2LG is well-suited for high-performance DSP because it combines approximately 1,150,000 logic elements with thousands of hardened floating-point DSP blocks delivering IEEE 754 single-precision arithmetic. Designers typically allocate DSP blocks for parallel FIR, FFT, and matrix-multiply kernels, while using M20K block memory for coefficient and sample buffering. According to the Intel Arria 10 datasheet, the -2 speed grade supports the mid-range fMAX required for radar, medical imaging, and machine-learning inference workloads, and the 768 user I/O pins provide ample LVDS pairs for ADC/DAC data interfaces.
Recommended
High-Speed Serial Protocol Bridging
The 10AX115N3F45I2LG fits high-speed serial protocol bridging because its transceivers support 28.05 Gbps with native PCIe Gen3, 10G/40G Ethernet, SATA, and CPRI hard IP. A common design is a PCIe Gen3 x8 endpoint to 10G/40G Ethernet gateway for HPC or storage applications, where the FPGA absorbs protocol translation in the high-density programmable fabric. The M20K block memory provides packet buffering, while the hardened PCIe Gen3 hard IP block reduces latency. According to Intel Arria 10 datasheet, this part supports OTN and Interlaken protocols through soft IP cores.
Recommended
Video Processing and Broadcast Pipelines
The 10AX115N3F45I2LG fits video processing and broadcast pipelines because its logic density supports multi-channel 4K/8K processing, format conversion, and low-latency color-space transforms in a single chip. The hardened floating-point DSP blocks accelerate motion estimation, deinterlacing, and HDR tone mapping. Designers use the 768 user I/O pins to interface SDI, HDMI 2.0, and DisplayPort interfaces via soft IP. According to the Intel Arria 10 datasheet, the -2 speed grade and M20K memory sustain multi-stream line buffers at UHD frame rates; the industrial temperature grade enables indoor broadcast rack deployments.
Recommended
Test and Measurement Instrumentation
The 10AX115N3F45I2LG is well-suited for test and measurement instrumentation because of its logic density, 28.05 Gbps transceivers, and hardened floating-point DSP. Designers can integrate arbitrary waveform generators, digital phosphor DSP, real-time spectrum analysis, and protocol-aware triggering in a single FPGA, reducing cost and footprint. The M20K block memory supports deep capture buffers, and the 768 user I/O pins handle parallel LVDS acquisition. According to Intel Arria 10 datasheet, the device's jitter performance and the -2 speed grade support tight acquisition timing budgets in lab-grade instruments.
Recommended
Aerospace and Defense Data Acquisition
The 10AX115N3F45I2LG suits aerospace and defense data acquisition because of its industrial temperature grade, high logic density, and hardened floating-point DSP for signal conditioning. Common uses include radar pre-processing, electronic-warfare channelization, and avionics data routing. The 28.05 Gbps transceivers support modern serial fabrics such as 10 Gb Ethernet and ARINC 818, while the M20K block memory absorbs sample bursts from multiple ADC channels. According to the Intel Arria 10 datasheet, the device's radiation-tolerant characteristics (when paired with mitigation IP) make it appropriate for airborne and naval deployments.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115N3F45I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115N3F45I2SG | 10AX115N3F45E2LG | 10AX115N2F45I2LG | 10AX115N3F40I2LG | 10AX090N3F45I2LG |
|---|---|---|---|---|---|---|
| Package | 1932-BBGA, FC-FBGA | 1932-BBGA, FC-FBGA - same | 1932-BBGA, FC-FBGA - same | 1932-BBGA, FC-FBGA - same | 1932-BBGA, FC-FBGA - same | 1932-BBGA, FC-FBGA - same |
| Brand | Intel | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 900,000 (-22%) |
| Speed Grade | -2 | -2 | -2 | -2 | -2 | -2 |
| Temperature Grade | Industrial (I) | Industrial (I) | Extended (E) | Industrial (I) | Industrial (I) | Industrial (I) |
| Transceivers | Up to 28.05 Gbps, ~12 channels | 28.05 Gbps, ~12 ch | 28.05 Gbps, ~12 ch | 28.05 Gbps, ~6 ch (-50%) | 28.05 Gbps, ~12 ch | 28.05 Gbps, ~12 ch |
| User I/O Pins | 768 | 768 | 768 | 768 | 768 | [DATA_NEEDED] |
| PCI Express Hard IP | Gen3 | Gen3 | Gen3 | Gen3 | Gen3 | Gen3 |
| Unit Price (USD, qty 1) | 9970.35 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest logic density in the Arria 10 GX family with 1,150,000 LEs (vs 10AX090N3F45I2LG)
- 12-channel transceiver count for full multi-protocol headroom (vs 10AX115N2F45I2LG)
- Industrial temperature range (-40C to +100C junction) for outdoor deployments (vs 10AX115N3F45E2LG)
- Hardened floating-point DSP blocks for high-throughput arithmetic (vs Smaller Cyclone 10 GX variants)
Design Notes
The 10AX115N3F45I2LG requires a multi-rail power tree: 0.9 V core (typically 8-15 A under load depending on utilization), 1.1 V / 1.8 V auxiliary, 2.5 V / 3.3 V I/O, and a separate PLL analog rail. According to the Intel Arria 10 datasheet, all rails must ramp within the Power-On Reset (POR) timing window; otherwise, the device enters an indeterminate state and requires a full power-off cycle. Designers should decouple each rail with bulk + 100 nF + 1 uF ceramic networks placed within 5 mm of the FC-FBGA balls. Use a high-performance PMBus controller such as the LTM4675 or TPS536C7 for adaptive voltage positioning.
Estimated: At full 1,150,000 LE utilization with the 12-channel transceiver active, total power dissipation can reach 25-40 W depending on clock and toggle rates. The FC-FBGA package requires a thermal pad with an array of thermal vias (0.3 mm pitch, 0.2 mm drill) stitched to internal copper planes. According to Intel Arria 10 thermal guidelines, designers must provide a continuous copper pour on top and bottom layers for spreading. Industrial-grade parts must keep the junction below 100 C; designers should verify the thermal model in Quartus Prime PowerPlay early in the project to size a heatsink or forced-air cooling.
The 1932-ball FC-FBGA package demands a high-layer-count PCB (typically 12-16 layers) with 0.8 mm or 1.0 mm ball pitch escape routing. Designers should use a 1-2-1 via-in-pad microvia stack under the BGA and follow Intel's signal-integrity guidelines for high-speed transceiver channels. Length-matching within a transceiver channel pair is typically required to within 0.05 mm. The reference clock and JTAG chain traces must be guarded against noise. According to the Intel Arria 10 datasheet, the high-speed serial channels require a tuned 100-ohm differential microstrip or stripline on a low-loss dielectric.
Do not assume 10AX115N3F45I2LG configuration is automatically preserved across power cycles: Active Serial (AS) configuration requires a valid EPCQ flash image that includes the correct device ID. According to the Intel Arria 10 datasheet, the configuration clock must be present before the CONF_DONE pin is sampled, and an unstable clock causes boot loops. Designers should always populate a JTAG header and confirm the Quartus Prime programmer sees the correct JTAG IDCODE (0x02FF) before relying on field updates. Also avoid mixing extended- and industrial-grade parts on the same PCB if your system spec requires industrial temperature at all positions.
Compliance Information
RoHS-compliant per Altera/Intel product page. Industrial temperature grade per Arria 10 datasheet. AEC-Q100 is not applicable for FPGAs in automotive safety-critical contexts - designers should consult Intel's automotive-grade Cyclone or Stratix lines for AEC-Q100 qualified parts.
