10CX085YF672E5G - Cyclone 10 GX 85K LE FPGA, 672-BGA | Intel
MPN: 10CX085YF672E5G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $412 | $412.00 |
| 10 | $385 | $3,850.00 |
| 100 | $348 | $34,800.00 |
| 500 | $318 | $159,000.00 |
| 1,000 | $289 | $289,000.00 |
Drop-in alternatives for 10CX085YF672E5G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10CX085YF672I5G
✅ Drop-In✓ In Stock
$19.78 / Unit
View Datasheet →10CX085YF672C8G
✅ Drop-In📋 Reference alternative (not in catalog)
10CX085YF672E6G
✅ Drop-In✓ In Stock
$280.5 / Unit
View Datasheet →10CX105YF672E5G
✅ Drop-In✓ In Stock
$310 / Unit
View Datasheet →10CX105YF672I5G
✅ Drop-In✓ In Stock
$108 / Unit
View Datasheet →10CX085YF672E5G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 GX |
| Logic Elements | 85,000 LE |
| Adaptive Logic Modules (ALMs) | 31,000 ALM |
| Embedded Memory | 5,959,680 bit (5.68 Mbit) |
| User I/Os | 192 (PCB source lists 212; datasheet top-mark variant dependent) |
| Package | 672-BGA (FBGA) |
| Process Technology | 20 nm |
| Operating Temperature | 0 °C to +100 °C (commercial, E5 grade) |
| Core Supply Voltage | 0.9 V |
| Transceivers | Up to 4 channels, 1.25–6.144 Gbps |
| Hard Memory Controller | DDR3 up to 933 MHz |
| DSP Blocks (18×19 Multipliers) | 156 |
| Mounting Type | Surface Mount (SMD/SMT) |
| RoHS Status | Compliant |
10CX085YF672E5G 672-bga (fbga) Pin Configuration Guide
Complete pinout information for 10CX085YF672E5G (672-bga (fbga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX085YF672E5G.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX085YF672E5G is suitable for 6 applications: Industrial Machine Vision Frame Grabber, Broadcast Video Processing Card, Telecom Backhaul Line Card, Low-Cost PCIe Expansion Card, Edge Inference Accelerator, Industrial IoT Gateway with Multi-Protocol Bridge.
Industrial Machine Vision Frame Grabber
The 10CX085YF672E5G's combination of 156 18×19 DSP multipliers and 5.68 Mbit embedded memory makes it a strong fit for cost-sensitive machine vision pipelines. Designers typically instantiate a CoaXpress or GigE Vision receiver in the transceiver PHY (data rates up to 6.144 Gbps), buffer full frames in the embedded M20K blocks, and run Bayer-to-RGB conversion plus defect-detection algorithms in the variable-precision DSP blocks. Compared with a CPU-only pipeline, the FPGA delivers 10× higher frame throughput at the same 12 W power budget, and the DDR3 controller sustains 933 MHz rates for line-scan sensor buffers.
Recommended
Broadcast Video Processing Card
For SDI and HDMI bridging, the 10CX085YF672E5G's 6.144 Gbps transceivers support 3G-SDI (SMPTE 424M) and reduced-rate 6G-SDI directly, while its 192 user I/Os expose sufficient LVDS pairs for HDMI 1.4 input or output. The 85K LE fabric is large enough to host a 4Kp60 video scaler, de-interlacer, and color-space converter simultaneously, and the 5.68 Mbit embedded memory absorbs up to four lines of vertical-tap filtering without external buffer cost. The 0.9 V core keeps typical board power around 6–8 W, allowing passive heatsinks in 1U chassis.
Recommended
Telecom Backhaul Line Card
Telecom backhaul cards using the 10CX085YF672E5G benefit from its hard PCIe Gen2 ×4 controller, which can connect directly to a host CPU or switch ASIC over a single PCIe lane pair, freeing all four transceivers for CPRI, OBSAI, or 10GBASE-R fronthaul links. The 85K LE fabric is sufficient to terminate 4 CPRI links (option 3) with on-chip re-mapping and to implement a small L2/L3 forwarding engine for aggregation scenarios. Hot-socketing support and industrial-grade silicon variants allow deployment in outdoor cabinets with ambient up to +100 °C.
Recommended
Low-Cost PCIe Expansion Card
For half-height PCIe x4 endpoint cards (data acquisition, software-defined radio, NVMe controller), the 10CX085YF672E5G offers a hard PCIe Gen2 controller that meets the 5 Gbps lane rate without consuming fabric resources. Designers can dedicate all 85K LE to user logic, supported by 4 lanes of 6.144 Gbps transceivers for ADC/DAC JESD204B interfaces. Power dissipation is significantly lower than a mid-range Arria 10 or Stratix 10 device, making the part popular for cost-optimised instrument cards.
Recommended
Edge Inference Accelerator
Although Cyclone 10 GX lacks hard AI tensor engines, the 10CX085YF672E5G's 156 DSP blocks deliver up to ~150 GMACs of INT8 throughput, sufficient for small CNN models such as MobileNet V2 at batch 1 with ~30 fps inference rates. The embedded memory (5.68 Mbit) caches layer weights for small models, while the DDR3 controller streams larger models from external DRAM. The low 0.9 V core voltage keeps total power around 4 W at full DSP utilization, suitable for fan-less edge appliances.
Recommended
Industrial IoT Gateway with Multi-Protocol Bridge
Industrial IoT gateways built on the 10CX085YF672E5G can aggregate field-bus traffic (PROFINET, EtherCAT, Modbus TCP) through the transceiver PHY while using the PCIe controller to present a deterministic endpoint to a host processor. The 192 user I/Os accept 24 LVDS pairs or 96 single-ended channels for legacy SPI, I2C, and UART fan-out. Hot-socketing and industrial-grade temperature options (-40 °C to +100 °C with the I5G variant) allow deployment in factory cabinets without active cooling.
Recommended
Recommended Products Summary
Engineering reference data for 10CX085YF672E5G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX085YF672I5G | 10CX085YF672C8G | 10CX085YF672E6G | 10CX105YF672E5G | 10CX105YF672I5G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-FBGA | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same | 672-FBGA - same |
| Logic Elements | 85,000 LE | 85,000 LE | 85,000 LE | 85,000 LE | 105,000 LE (+24%) | 105,000 LE (+24%) |
| Embedded Memory | 5.68 Mbit | 5.68 Mbit | 5.68 Mbit | 5.68 Mbit | 5.68 Mbit | 5.68 Mbit |
| Transceivers | 4 ch × 6.144 Gbps | 4 ch × 6.144 Gbps | 4 ch × 6.144 Gbps | 4 ch × 6.144 Gbps | 6 ch × 6.144 Gbps | 6 ch × 6.144 Gbps |
| Operating Temperature | 0 °C to +100 °C | -40 °C to +100 °C (industrial) | 0 °C to +100 °C | 0 °C to +100 °C | 0 °C to +100 °C | -40 °C to +100 °C (industrial) |
| Speed Grade | 5 (mid) | 5 | 8 (slower) | 6 (faster) | 5 | 5 |
| Hard PCIe Gen2 | Yes (×4) | Yes (×4) | Yes (×4) | Yes (×4) | Yes (×4) | Yes (×4) |
| Unit Price (qty 1) | $412 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Higher logic density than Cyclone 10 LP in the same family tier (vs 10CL120YF780I7G)
- Lower cost than Arria 10 for transceiver-based designs (vs 10AX115N2F45E1SG (Arria 10))
- Modern 20 nm process vs 28 nm Cyclone V (vs 5CGXFC7C7F23C8N (Cyclone V GX))
Design Notes
Use a minimum 4-layer stack-up with continuous GND on layer 2 and PWR on layer 3 directly beneath the 672-BGA. Recommended: JEDEC JESD51-9 1.0 mm pitch BGA land pattern with NSMD pads 0.4 mm diameter and 0.5 mm solder mask openings. Estimated: 168 of the 672 balls are GND, so the PCB should dedicate at least 25% of the BGA footprint shadow to via-in-pad microvias for thermal and signal return.
Follow Intel's Cyclone 10 GX power distribution network (PDN) guideline: place one 0.1 µF X7R 0402 capacitor and one 1 µF X5R 0603 capacitor within 5 mm of every VCC pin group, plus one 10 µF bulk capacitor per voltage rail near the BGA. Estimated: total decoupling count ~120 ceramic capacitors for a fully populated 672-FBGA design. Use Intel's Early Power Estimator (EPE) tool to validate static and dynamic power before PCB commitment.
At typical utilization (~70% LE, ~80% DSP, all 4 transceivers active), the 10CX085YF672E5G dissipates approximately 5–7 W. With the 672-FBGA package theta_JA of ~12 °C/W (still air, JEDEC test board), junction temperature rise is ~60–85 °C. Recommended: connect the central 64 thermal balls to a 10×10 mm copper coin on the top layer and add 4 thermal vias to internal GND plane; this reduces junction-to-ambient resistance to ~8 °C/W.
Transceiver channel traces must be length-matched within ±150 µm and routed only on the top layer over a continuous GND plane, with no vias on the differential pair. Each transceiver lane requires its own AC-coupling capacitor (0.1 µF 0201) within 5 mm of the FPGA ball. Reference clock lines require 50 Ω controlled impedance and isolation from data lines by at least 3× dielectric height. Consult AN-808 document for full transceiver layout guidelines.
Do not connect JTAG TCK, TMS, TDI, TDO signals without 4.7 kΩ pull-ups on TMS and TDI per Intel recommendation; missing pull-ups cause configuration failures on power-up. The CONF_DONE pin must be monitored by the host CPU via a 4.7 kΩ pull-up to VCCIO for safe multi-FPGA configuration sequencing. Avoid using the MSEL pins as user I/O - they are sampled at power-up and must be tied to fixed logic levels.
Compliance Information
RoHS and REACH compliant per Intel Cyclone 10 GX material declaration. AEC-Q100 not applicable for commercial-grade FPGA. Lead-free BGA balls (SAC405). Halogen-free per JEDEC JS709B. Conflict-mineral reporting compliant under the Intel CMRT framework.
