10CX085YF672I5G - 85K LE Cyclone 10 GX FPGA, 672-BGA | Intel
MPN: 10CX085YF672I5G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $168.5 | $168.50 |
| 10 | $152.2 | $1,522.00 |
| 100 | $132.8 | $13,280.00 |
| 500 | $112.4 | $56,200.00 |
| 1,000 | $95.6 | $95,600.00 |
10CX085YF672I5G Overview
A field-programmable gate array (FPGA) is a reprogrammable semiconductor device that combines configurable logic blocks (CLBs), programmable routing fabric, and hardened silicon IP (memory, DSP, transceivers, PCIe) to implement custom digital logic. Within the broader taxonomy, an FPGA is a programmable logic device (PLD) under the category of programmable logic ICs, which also includes Complex PLDs (CPLDs) and Structured ASICs. Cyclone 10 GX sits in the low-power, transceiver-equipped tier of Intel's FPGA portfolio, below Arria 10 and Stratix 10, and is designed for high-volume cost-sensitive designs.
Key differentiating features include 31,000 adaptive logic modules (ALMs) with 6-input LUTs, 5.68 Mbit embedded memory, 1.4 GHz LVDS operation, and PCI Express Gen2 hard IP blocks. The FBGA672 package is one of the larger members of the Cyclone 10 GX family and offers the highest user I/O count available on this die, while exposing 10-Gbps-capable transceivers on supported variants. The combination of 85000 logic elements and 31000 ALMs positions 10CX085YF672I5G as the mid-density option in the 10CX085 line.
Typical applications span industrial machine vision, broadcast video processing, low-cost wireline backplanes, motor and motion control, and PCI Express Gen2 endpoint cards. The wide I/O bandwidth and hardened memory controllers also make the device suitable for multi-camera capture and protocol bridging in factory-automation systems. Quartus Prime software supports full synthesis, place-and-route, and timing closure for this part.
When designing with this device, allocate sufficient PCB area for the 27 mm x 27 mm FBGA672 footprint and follow Intel's power-rail sequencing recommendations. Use a multi-layer PCB with dedicated ground and power planes, and pair the device with low-noise LDO regulators for analog and transceiver supply rails. Ensure thermal vias are placed under the exposed die pad to manage the ~10-15 W typical dissipation in transceiver-heavy designs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single reference for selecting and sourcing the 10CX085YF672I5G.
Drop-in alternatives for 10CX085YF672I5G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with 10CX085YF672I5G (same form factor and footprint) — differing in Package, Mounting Type, Operating Temperature, Embedded Memory, Logic Elements (LE).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10CX085YF672I6G
✅ Drop-In✓ In Stock
$255 / Unit
View Datasheet →10CX085YF672I7G
✅ Drop-In📋 Reference alternative (not in catalog)
10CX105YF672I5G
✅ Drop-In✓ In Stock
$108 / Unit
View Datasheet →10CX220YF672I5G
✅ Drop-In✓ In Stock
$600 / Unit
View Datasheet →10CL055YF672I5G
✅ Drop-In📋 Reference alternative (not in catalog)
EP4CE85F672I5N
✅ Drop-In📋 Reference alternative (not in catalog)
10CX085YF672I5G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 GX |
| Family | Cyclone 10 GX (10CX085) |
| Logic Elements (LE) | 85000 |
| Adaptive Logic Modules (ALM) | 31000 |
| ALM Inputs per ALM | 6 |
| Embedded Memory | 5959680 bits (5.68 Mbit) |
| 18x18 Multipliers | 216 |
| User I/Os | 192 |
| Package | 672-BGA (FBGA672) |
| Process Technology | TSMC 20 nm |
| Maximum Supply Voltage | 0.93 V |
| Operating Temperature | -40C to +85C (Industrial) |
| Speed Grade | 5 |
| LVDS Data Rate | 1.4 Gbps (up to 1.866 Gbps with enhanced I/O) |
| Mounting Type | Surface Mount (FBGA) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Recommended Tool | Quartus Prime |
10CX085YF672I5G 672-bga (fbga672) Pin Configuration Guide
Pin configuration for 10CX085YF672I5G (672-bga (fbga672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX085YF672I5G.
Refer to the datasheet for full pin configuration.
Typical Applications
10CX085YF672I5G is suitable for 6 applications: Industrial Machine Vision, Broadcast Video Processing, PCI Express Endpoint Card, Motor and Motion Control, Low-Cost Wireline Backplane, Protocol Bridging in Factory Automation.
Industrial Machine Vision
The 10CX085YF672I5G fits industrial machine vision because its 85,000 logic elements and 216 18x18 multipliers deliver 1080p60 image-processing throughput with headroom for GigE Vision or CoaXPress protocol stacks. The FBGA672's 192 user I/Os expose multiple LVDS lanes at 1.4 Gbps for direct image-sensor interfacing, while the 5.68 Mbit embedded memory acts as line buffer and statistics accumulator without external SRAM. Unlike discrete DSP + MCU architectures, the integrated PCIe Gen2 hard IP enables single-chip connection to host PCs, reducing BOM and latency in vision-guided robotics and AOI inspection systems on factory floors.
Recommended
Broadcast Video Processing
The 10CX085YF672I5G suits broadcast video processing because its 85K logic elements and 216 DSP blocks handle 3G-SDI input aggregation, scaling, and deinterlacing at 1080p60 with sub-frame latency. The 192 user I/Os in FBGA672 connect to multiple SDI deserializer/serializer pairs at 1.4 Gbps LVDS, while PCIe Gen2 hard IP links to capture or playout host cards. Compared to ASIC + external FPGA designs, integrating transport stream parsing, color space conversion, and audio embedding on one chip reduces PCB complexity, power, and BOM cost for broadcast routers and contribution encoders.
Recommended
PCI Express Endpoint Card
The 10CX085YF672I5G fits PCIe Gen2 endpoint designs because its integrated Gen2 hard IP block provides x1/x2/x4 lane support without consuming logic elements. The 85K logic elements and 5.68 Mbit embedded memory implement DMA engines, MSI-X interrupt tables, and protocol logic for data acquisition cards, while the FBGA672's 192 user I/Os fan out to FMC connectors or on-board ADCs/DACs. Trade-off vs higher-end Stratix 10: 10CX085YF672I5G cuts unit cost by ~60% at slightly lower Fmax, making it the sweet-spot for cost-sensitive PCIe data capture and DSP accelerator cards.
Recommended
Motor and Motion Control
The 10CX085YF672I5G suits motor and motion control because its 85,000 logic elements and 216 18x18 multipliers compute Field-Oriented Control (FOC) loops and SVPWM modulation for multi-axis servo drives. The 192 user I/Os in FBGA672 connect to multiple encoder inputs (EnDat, BISS, TTL) and PWM outputs, while PCIe Gen2 enables connection to industrial PCs or EtherCAT bridges. Compared to MCU-only architectures, integrating position, velocity, and current loops on one Cyclone 10 GX gives sub-microsecond loop times, deterministic jitter, and faster system tuning.
Recommended
Low-Cost Wireline Backplane
The 10CX085YF672I5G fits low-cost wireline backplane aggregation because its FBGA672 package exposes the full transceiver count and 192 user I/Os for protocol-bridging between SFP+, KR, and backplane SerDes. The 85K logic elements implement PCS/MAC adaptation for CPRI, OBSAI, or proprietary protocols without external ASSPs, while PCIe Gen2 enables switch-fabric connectivity. Trade-off vs higher-tier Arria 10: 10CX085YF672I5G cuts BOM cost by ~50% for 5G fronthaul and small-cell baseband aggregation where full transceiver count matters but per-channel Fmax does not.
Recommended
Protocol Bridging in Factory Automation
The 10CX085YF672I5G fits protocol bridging in factory automation because its 85,000 logic elements and 5.68 Mbit embedded memory translate between PROFINET, EtherCAT, EtherNet/IP, and proprietary fieldbus protocols on a single chip. The FBGA672's 192 user I/Os connect to multiple PHY interfaces and isolated RS-485 ports, while the integrated PCIe Gen2 hard IP links to industrial PCs for HMI integration. Trade-off vs MCU + ASSP stacks: integrating the entire protocol bridge on one Cyclone 10 GX eliminates firmware overhead, ensures deterministic latency, and reduces BOM in PLC and distributed I/O designs.
Recommended
Recommended Products Summary
Engineering reference data for 10CX085YF672I5G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX085YF672I6G | 10CX085YF672I7G | 10CX105YF672I5G | 10CX220YF672I5G | 10CL055YF672I5G | EP4CE85F672I5N |
|---|---|---|---|---|---|---|---|
| Package | FBGA-672 (F672) | FBGA-672 (F672) - same | FBGA-672 (F672) - same | FBGA-672 (F672) - same | FBGA-672 (F672) - same | FBGA-672 (F672) - same | FBGA-672 (F672) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Series | Cyclone 10 GX | Cyclone 10 GX | Cyclone 10 GX | Cyclone 10 GX | Cyclone 10 GX | Cyclone 10 LP | Cyclone IV E |
| Logic Elements | 85000 | 85000 (same) | 85000 (same) | 105000 (+24%) | 220000 (+159%) | 55000 (-35%) | 85000 (same) |
| User I/Os | 192 | 192 (same) | 192 (same) | 192 (same) | 192 (same) | 192 (same) | 192 (same) |
| Transceivers | Yes (10 Gbps-capable) | Yes (same) | Yes (same) | Yes (same) | Yes (same) | No | No |
| Embedded Memory | 5.68 Mbit | 5.68 Mbit (same) | 5.68 Mbit (same) | 6.85 Mbit (+21%) | 13.94 Mbit (+145%) | 1.65 Mbit (-71%) | 4.65 Mbit (-18%) |
| 18x18 Multipliers | 216 | 216 (same) | 216 (same) | 270 (+25%) | 534 (+147%) | 150 (-31%) | 238 (+10%) |
| Process Technology | 20 nm TSMC | 20 nm (same) | 20 nm (same) | 20 nm (same) | 20 nm (same) | 60 nm | 60 nm |
Key Differentiators
- Highest-density package option for the 10CX085 die (vs 10CX085YF484I5G)
- Integrated PCIe Gen2 hard IP block (vs 10CL055YF672I5G (Cyclone 10 LP))
- 20 nm TSMC process for higher Fmax and lower power (vs EP4CE85F672I5N (Cyclone IV E))
- Mid-density sweet spot in the Cyclone 10 GX family (vs 10CX105YF672I5G)
Design Notes
The FBGA672 package requires a 27 mm x 27 mm PCB land pattern with 1.0 mm ball pitch. Use at least 6 PCB layers with dedicated ground and power planes. Place thermal vias (0.2 mm drill, 0.4 mm pad, 1.0 mm pitch) directly under the exposed die to manage the typical 8-12 W dissipation under transceiver load. Reference Intel's Cyclone 10 GX hardware user guide for trace routing, length matching, and via stitching recommendations.
Power the 10CX085YF672I5G with the Intel-recommended power sequencer (e.g., EM11x or LTC3612 family) to control core (0.93 V), I/O bank, and transceiver rails. Estimated: at full load with 12 transceiver channels active, the device draws approximately 8-12 W total; this requires a multi-phase regulator and substantial copper pours on the 0.93 V core rail. Do not skip the POR delay circuit or the device may fail to configure on cold start.
Estimated: at 25C ambient with 10 W dissipation, the FBGA672 junction-to-ambient thermal resistance (theta_JA) of ~8 C/W with proper thermal vias gives a 25C junction rise. For industrial-grade designs at 85C ambient, derate transceiver channel count by 20-30% to keep Tj under 100C. Always verify with a thermal camera on the final prototype, especially for sealed industrial enclosures with no airflow.
Transceiver channels at 10 Gbps require controlled-impedance differential routing (100 ohm +/- 10%) on the top layer with continuous ground reference below. Keep PCB stubs under 0.5 mm and use matched-length routing (within 0.1 mm) per pair. For LVDS pairs at 1.4 Gbps, follow the LVDS I/O bank configuration in the Cyclone 10 GX family datasheet to avoid signal integrity issues. Always simulate the channel with the Quartus Prime SignalTap and IBIS-AMI models before tape-out.
Do not power up the 10CX085YF672I5G with the JTAG header connected to a powered programmer - the device may latch into configuration mode and refuse to boot. Always deassert the nCONFIG pin after power-rail stabilization. Avoid mixing 1.5 V and 1.8 V I/O bank supplies on the same bank - the device can latch up. Use Quartus Prime 18.1 or later for full Cyclone 10 GX support, and pin the design to avoid I/O bank rule violations on LVDS pairs.
Compliance Information
RoHS and REACH compliance per Intel Cyclone 10 GX product page. AEC-Q100 not applicable for FPGAs in industrial temperature grade; this part is industrial-grade (-40C to +85C), not automotive-qualified. Lead-free BGA balls per JEDEC J-STD-020.
