A42MX36-1PQG208 - 54K Gate FPGA, 176 I/O | Microchip
MPN: A42MX36-1PQG208 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $68.5 | $68.50 |
| 10 | $62.1 | $621.00 |
| 100 | $55.8 | $5,580.00 |
| 500 | $50.2 | $25,100.00 |
| 1,000 | $45.3 | $45,300.00 |
Drop-in alternatives for A42MX36-1PQG208 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
A42MX36-PQG208I
β Drop-Inβ In Stock
$55 / Unit
View Datasheet βA42MX36-1PQG208M
β Drop-Inπ Reference alternative (not in catalog)
A42MX36-PQ208I
β Drop-Inπ Reference alternative (not in catalog)
A42MX36PQ208-1M
β Drop-Inβ In Stock
$29 / Unit
View Datasheet βA42MX36-1PQG208X39
β Drop-Inπ Reference alternative (not in catalog)
XC5206-5PQG208C
β Drop-Inπ Reference alternative (not in catalog)
XC3195A-3PQ208I
β Drop-Inπ Reference alternative (not in catalog)
A42MX36-1PQG208 Maximum Ratings & Electrical Characteristics
| Family | MX (42MX) |
| System Gates | 54000 |
| Configurable Logic Blocks (CLBs) | 1184 |
| Logic Modules | 2560 |
| User I/O | 176 |
| Speed Grade | -1 (standard) |
| Supply Voltage | 3.3 V / 5 V |
| Technology | CMOS, 0.45 um class |
| Embedded Memory | Dual-port SRAM modules (FIFO/LIFO/scratchpad) |
| Special Modules | Wide-decode modules |
| PCI Compliance | PCI Local Bus Specification v2.1 |
| I/O Features | MultiPlex I/O, mixed-voltage, low-power mode |
| Package | 208-BFQFP (PQFP), 28 x 28 mm |
| Mounting Type | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] |
| Configuration | Non-volatile, single-chip (no external boot flash) |
| RoHS Status | Compliant (G suffix = lead-free) |
A42MX36-1PQG208 Pin Configuration
| Pin 1 | GND β Ground reference |
| Pin 12 | VCC β Core supply voltage |
| Pin 24 | VCCA β Analog/auxiliary supply |
| Pin 37 | IO β MultiPlex user I/O (5V tolerant) |
| Pin 53 | CLK β Global clock input |
| Pin 70 | RESET β Global reset input |
| Pin 92 | IO β MultiPlex user I/O |
| Pin 115 | VCC β Core supply voltage |
| Pin 140 | IO β MultiPlex user I/O |
| Pin 168 | GND β Ground reference |
| Pin 190 | IO β MultiPlex user I/O |
| Pin 208 | IO/VCC β User I/O or supply per datasheet pin table |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX36-1PQG208 is suitable for 6 applications: Legacy PLD / Glue Logic Consolidation, PCI Interface Bridging, Industrial Control Systems, Mil/Aerospace Systems, FIFO / Data Path Buffering, Test and Measurement Instrumentation.
Legacy PLD / Glue Logic Consolidation
The A42MX36-1PQG208's 54,000 gates and 1184 CLBs allow designers to consolidate multiple legacy PLDs, PALs, and discrete glue logic into a single non-volatile chip. The MultiPlex I/O with 5.0V/3.3V tolerance directly interfaces with older 5V bus systems without level shifting, and the single-chip configuration removes boot PROMs. Wide-decode modules handle high-fan-in address decoding efficiently, making migration of decades-old board designs straightforward.
Recommended
PCI Interface Bridging
Per the 40MX/42MX datasheet, the A42MX36 is fully compliant with the PCI Local Bus Specification version 2.1, supporting programmable PCI at 5.0V and 3.3V signaling. The 176 MultiPlex I/O pins supply enough capacity for a full 32-bit PCI master/target implementation plus application logic, while the -1 speed grade meets 33 MHz PCI timing. Non-volatile configuration ensures the bridge is active immediately at power-up, simplifying system bring-up.
Recommended
Industrial Control Systems
In industrial automation, the A42MX36-1PQG208 provides deterministic programmable logic with 5V-tolerant I/O for sensors, actuators, and legacy PLC backplanes. Its non-volatile antifuse-class configuration survives power cycling without reconfiguration hardware, and the low-power mode reduces consumption in always-on installations. Dual-port SRAM blocks implement ping-pong buffers between control processors and field I/O, and the 208-PQFP industrial variants (I suffix) cover extended temperature deployments.
Recommended
Mil/Aerospace Systems
The MX family's ceramic packaging options make the A42MX36 attractive for defense and aerospace. Per the FPGAkey family reference, the CQ208 and PQ208 devices are pin-compatible, enabling prototyping in plastic and production conversion to MIL-STD-883 screened ceramic packages without PCB changes. The non-volatile single-chip configuration offers inherent resistance to configuration upsets and readback, and the M-suffix variants (A42MX36-1PQG208M) address military screening requirements.
Recommended
FIFO / Data Path Buffering
The A42MX36's embedded dual-port SRAM modules are optimized for high-speed datapath functions such as FIFOs, LIFOs, and scratchpad memory. Using the ACTgen Macro Builder in Microsemi Designer software, engineers instantiate FIFO queues of configurable width and depth without consuming general-purpose logic modules. This suits instrumentation, imaging, and communications boards that need independent read/write clock domains between acquisition front ends and processing elements.
Recommended
Test and Measurement Instrumentation
The A42MX36-1PQG208 implements timing generators, trigger logic, and protocol decoders in test equipment, where the 176 user I/O connect to front-panel interfaces and measurement front ends. Non-volatile configuration means the instrument is functional the instant power is applied, and the 5.0V/3.3V MultiPlex I/O supports both legacy and modern probe interface standards. The -1 speed grade comfortably serves state-machine and decode paths in the tens of MHz range.
Recommended
Recommended Products Summary
Engineering reference data for A42MX36-1PQG208 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX36-PQG208I | A42MX36-1PQG208M | XC5206-5PQG208C | XC3195A-3PQ208I |
|---|---|---|---|---|---|
| Package | 208-BFQFP (PQFP) | 208-PQFP - same | 208-BFQFP - same | 208-PQFP - same footprint | 208-PQFP - same footprint |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Xilinx | Xilinx |
| System Gates | 54,000 | 54,000 | 54,000 | [DATA_NEEDED] | [DATA_NEEDED] |
| User I/O | 176 | 176 | 176 | [DATA_NEEDED] | [DATA_NEEDED] |
| Supply Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 5 V (G suffix lead-free) | 5 V |
| Temperature Grade | Standard (commercial/industrial per suffix -1) | Industrial (I) | Military-screened (M) | Commercial (C) | Industrial (I) |
| Configuration | Non-volatile, single-chip | Non-volatile, single-chip | Non-volatile, single-chip | SRAM-based (external config) | SRAM-based (external config) |
| Embedded SRAM | Dual-port SRAM + wide-decode modules | Dual-port SRAM - same | Dual-port SRAM - same | Distributed LUT RAM | None (no block RAM) |
Key Differentiators
- Non-volatile single-chip configuration (vs XC5206-5PQG208C)
- Dual-port embedded SRAM blocks (vs XC3195A-3PQ208I)
- Ceramic-package migration path (vs A42MX36-PQG208I)
Design Notes
The A42MX36 uses separate VCC and VCCA supply pins in the 208-PQFP. Follow the 40MX/42MX datasheet (DS2136) power sequencing guidance: apply VCCA and VCC per the recommended order and decouple each supply pin with 0.1uF ceramics placed within 2 mm of the pin, plus bulk 10uF per rail. Mixed 3.3V/5.0V I/O banking requires each I/O bank's supply to match its signaling standard - never drive a 3.3V-configured bank from 5V logic.
The 208-pin PQFP has 0.5 mm pitch leads requiring fine-pitch soldering: use solder paste printing verified for 0.5 mm apertures and inspect with X-ray or AOI for bridging on the perimeter rows. The plastic PQ208 footprint is identical to the CQ208 ceramic package, so design the PCB once and switch to ceramic for mil/aero builds without re-layout, per the FPGAkey family reference.
The -1 speed grade is the slowest MX option - do timing closure in Microsemi Designer software before committing to PCB fab, especially for PCI v2.1 designs where 33 MHz setup/hold must be met. Do not assume SRAM-based Xilinx cross-references (XC5206, XC3195A) are drop-in: they need external configuration devices and different pin assignments. Also confirm lead finish requirements (G = lead-free vs non-G) for your compliance program.
Compliance Information
G suffix in PQG208 denotes lead-free finish per Microchip/Microsemi naming. Lisleapex listing confirms LEAD FREE. ECCN 3A991.d.2 per legacy Microsemi records.
