EPF8820ATC144-6 - 8K Gates, 125MHz FLEX 8000 FPGA | Altera
MPN: EPF8820ATC144-6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.95 | $249.50 |
| 100 | $19.4 | $1,940.00 |
| 500 | $15.85 | $7,925.00 |
| 1,000 | $12.3 | $12,300.00 |
Drop-in alternatives for EPF8820ATC144-6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF8820ATC144-4N
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View Datasheet →EPF8820ATC144-4
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View Datasheet →EPF8820ATC144-3N
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View Datasheet →EPF8820ATC144-3
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$9.25 / Unit
View Datasheet →EPF8820ATC144-2N
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$18.95 / Unit
View Datasheet →EPF8820ATC144-2
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View Datasheet →EPF8820ATC144-6 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Series | EPF8820A |
| Usable Gates | ~8,000 |
| Logic Cells | 672 |
| Logic Array Blocks (LABs) | 84 |
| User I/Os | 112 |
| Dedicated Inputs | 4 |
| Supply Voltage | 5 V |
| I/O Standards | 3.3 V / 5.0 V MultiVolt (144-pin packages) |
| Internal Frequency | 125 MHz |
| Speed Grade | -6 (slowest commercial) |
| Configuration Memory | CMOS SRAM |
| Package | 144-pin TQFP (LFQFP), 0.5 mm pitch |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
| Configuration Device Options | EPC1, EPC1213, EPC1064, EPC1441 |
| In-Circuit Reconfigurability | Yes |
EPF8820ATC144-6 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | VCCINT — Internal core supply (5V) |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | GND — Ground |
| Pin 15 | I/O — User I/O pin (bank 2) |
| Pin 16 | I/O — User I/O pin (bank 2) |
| Pin 17 | I/O — User I/O pin (bank 2) |
| Pin 18 | I/O — User I/O pin (bank 2) |
| Pin 19 | I/O — User I/O pin (bank 2) |
| Pin 20 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 21 | I/O — User I/O pin (bank 2) |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | I/O — User I/O pin (bank 2) |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | I/O — User I/O pin (bank 2) |
| Pin 26 | GND — Ground |
| Pin 27 | I/O — User I/O pin (bank 3) |
| Pin 28 | I/O — User I/O pin (bank 3) |
| Pin 29 | I/O — User I/O pin (bank 3) |
| Pin 30 | I/O — User I/O pin (bank 3) |
| Pin 31 | I/O — User I/O pin (bank 3) |
| Pin 32 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 33 | I/O — User I/O pin (bank 3) |
| Pin 34 | I/O — User I/O pin (bank 3) |
| Pin 35 | I/O — User I/O pin (bank 3) |
| Pin 36 | I/O — User I/O pin (bank 3) |
| Pin 37 | I/O — User I/O pin (bank 3) |
| Pin 38 | GND — Ground |
| Pin 39 | I/O — User I/O pin (bank 4) |
| Pin 40 | I/O — User I/O pin (bank 4) |
| Pin 41 | I/O — User I/O pin (bank 4) |
| Pin 42 | I/O — User I/O pin (bank 4) |
| Pin 43 | I/O — User I/O pin (bank 4) |
| Pin 44 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 45 | I/O — User I/O pin (bank 4) |
| Pin 46 | I/O — User I/O pin (bank 4) |
| Pin 47 | I/O — User I/O pin (bank 4) |
| Pin 48 | I/O — User I/O pin (bank 4) |
| Pin 49 | I/O — User I/O pin (bank 4) |
| Pin 50 | GND — Ground |
| Pin 51 | I/O — User I/O pin (bank 5) |
| Pin 52 | I/O — User I/O pin (bank 5) |
| Pin 53 | I/O — User I/O pin (bank 5) |
| Pin 54 | I/O — User I/O pin (bank 5) |
| Pin 55 | I/O — User I/O pin (bank 5) |
| Pin 56 | VCCINT — Internal core supply (5V) |
| Pin 57 | I/O — User I/O pin (bank 5) |
| Pin 58 | I/O — User I/O pin (bank 5) |
| Pin 59 | I/O — User I/O pin (bank 5) |
| Pin 60 | I/O — User I/O pin (bank 5) |
| Pin 61 | I/O — User I/O pin (bank 5) |
| Pin 62 | GND — Ground |
| Pin 63 | I/O — User I/O pin (bank 6) |
| Pin 64 | I/O — User I/O pin (bank 6) |
| Pin 65 | I/O — User I/O pin (bank 6) |
| Pin 66 | I/O — User I/O pin (bank 6) |
| Pin 67 | I/O — User I/O pin (bank 6) |
| Pin 68 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 69 | I/O — User I/O pin (bank 6) |
| Pin 70 | I/O — User I/O pin (bank 6) |
| Pin 71 | I/O — User I/O pin (bank 6) |
| Pin 72 | I/O — User I/O pin (bank 6) |
| Pin 73 | I/O — User I/O pin (bank 6) |
| Pin 74 | GND — Ground |
| Pin 75 | I/O — User I/O pin (bank 7) |
| Pin 76 | I/O — User I/O pin (bank 7) |
| Pin 77 | I/O — User I/O pin (bank 7) |
| Pin 78 | I/O — User I/O pin (bank 7) |
| Pin 79 | I/O — User I/O pin (bank 7) |
| Pin 80 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 81 | I/O — User I/O pin (bank 7) |
| Pin 82 | I/O — User I/O pin (bank 7) |
| Pin 83 | I/O — User I/O pin (bank 7) |
| Pin 84 | I/O — User I/O pin (bank 7) |
| Pin 85 | I/O — User I/O pin (bank 7) |
| Pin 86 | GND — Ground |
| Pin 87 | I/O — User I/O pin (bank 8) |
| Pin 88 | I/O — User I/O pin (bank 8) |
| Pin 89 | I/O — User I/O pin (bank 8) |
| Pin 90 | I/O — User I/O pin (bank 8) |
| Pin 91 | I/O — User I/O pin (bank 8) |
| Pin 92 | VCCINT — Internal core supply (5V) |
| Pin 93 | I/O — User I/O pin (bank 8) |
| Pin 94 | I/O — User I/O pin (bank 8) |
| Pin 95 | I/O — User I/O pin (bank 8) |
| Pin 96 | I/O — User I/O pin (bank 8) |
| Pin 97 | I/O — User I/O pin (bank 8) |
| Pin 98 | GND — Ground |
| Pin 99 | I/O — User I/O pin (bank 1) |
| Pin 100 | I/O — User I/O pin (bank 1) |
| Pin 101 | I/O — User I/O pin (bank 1) |
| Pin 102 | I/O — User I/O pin (bank 1) |
| Pin 103 | nCONFIG — Configuration control (active low) |
| Pin 104 | nSTATUS — Configuration status (active low) |
| Pin 105 | CONF_DONE — Configuration done indicator |
| Pin 106 | DCLK — Configuration clock input |
| Pin 107 | DATA0 — Configuration data input |
| Pin 108 | MSEL0 — Configuration mode select 0 |
| Pin 109 | MSEL1 — Configuration mode select 1 |
| Pin 110 | GND — Ground |
| Pin 111 | DEV_OE — Device-wide output enable |
| Pin 112 | DEV_CLR — Device-wide register clear |
| Pin 113 | TDI — JTAG test data input |
| Pin 114 | TDO — JTAG test data output |
| Pin 115 | TMS — JTAG test mode select |
| Pin 116 | TCK — JTAG test clock |
| Pin 117 | I/O — User I/O pin (bank 1) |
| Pin 118 | I/O — User I/O pin (bank 1) |
| Pin 119 | I/O — User I/O pin (bank 1) |
| Pin 120 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 121 | I/O — User I/O pin (bank 1) |
| Pin 122 | I/O — User I/O pin (bank 1) |
| Pin 123 | I/O — User I/O pin (bank 1) |
| Pin 124 | I/O — User I/O pin (bank 1) |
| Pin 125 | I/O — User I/O pin (bank 1) |
| Pin 126 | GND — Ground |
| Pin 127 | INPUT — Dedicated input pin 1 |
| Pin 128 | INPUT — Dedicated input pin 2 |
| Pin 129 | INPUT — Dedicated input pin 3 |
| Pin 130 | INPUT — Dedicated input pin 4 |
| Pin 131 | I/O — User I/O pin (bank 2) |
| Pin 132 | I/O — User I/O pin (bank 2) |
| Pin 133 | I/O — User I/O pin (bank 2) |
| Pin 134 | I/O — User I/O pin (bank 2) |
| Pin 135 | I/O — User I/O pin (bank 2) |
| Pin 136 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 137 | I/O — User I/O pin (bank 2) |
| Pin 138 | I/O — User I/O pin (bank 2) |
| Pin 139 | I/O — User I/O pin (bank 2) |
| Pin 140 | I/O — User I/O pin (bank 2) |
| Pin 141 | I/O — User I/O pin (bank 2) |
| Pin 142 | GND — Ground |
| Pin 143 | I/O — User I/O pin (bank 2) |
| Pin 144 | I/O — User I/O pin (bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820ATC144-6 is suitable for 6 applications: PCI / ISA Bus Interface Bridging, Industrial Glue-Logic Consolidation, Address Decoding and Interrupt Handling, Legacy 5V Peripheral Interfacing, State-Machine Replacement in Embedded Controllers, VME Bus Interface in Legacy Industrial Systems.
PCI / ISA Bus Interface Bridging
The EPF8820ATC144-6's 112 user I/Os and 5V-tolerant MultiVolt interface make it well suited for PCI and ISA bus bridging in legacy industrial PCs. Its 672 logic cells accommodate full 32-bit address/data multiplexing, command decoding, and wait-state generation without external TTL glue. The 144-pin LFQFP exposes enough I/O for both the primary and secondary bus sides plus configuration pins. The -6 speed grade is acceptable for 33MHz PCI and full-speed ISA, where 1.9ns propagation delay leaves adequate timing margin over a 30ns bus cycle. For new designs, migrate to a Cyclone series FPGA with PCI Express hard IP.
Recommended
Industrial Glue-Logic Consolidation
The EPF8820ATC144-6 consolidates dozens of 74-series logic packages into a single 144-pin LFQFP, saving substantial PCB area in industrial controllers and PLCs. Its 8,000 usable gates handle wide address decoding, interrupt controllers, watchdog timers, and parallel-to-serial converters in one device. The 5V VCCINT plus MultiVolt I/O (3.3V or 5.0V on 144-pin packages) lets it interface directly with 5V microcontrollers and legacy peripherals, eliminating level shifters. In-circuit reconfigurability enables field firmware updates via the JTAG or serial configuration interface. Choose the -4 grade when timing closure is critical; -6 is sufficient for most glue-logic paths under 50MHz.
Recommended
Address Decoding and Interrupt Handling
The EPF8820ATC144-6 is well suited for memory and peripheral address decoding plus interrupt prioritization in 16/32-bit embedded systems. Each LAB provides eight logic elements plus product-term expansion, ideal for wide decoder trees and priority encoders. With 84 LABs and 672 logic cells, a single device can replace several PAL/GAL devices and discrete priority logic. The 112 user I/Os accommodate full 32-bit address buses plus chip-select outputs, interrupt request inputs, and acknowledge outputs. SRAM-based configuration allows last-minute design changes without respinning the PCB. The -6 speed grade supports up to 125MHz internal frequency, sufficient for most embedded address cycles.
Recommended
Legacy 5V Peripheral Interfacing
The EPF8820ATC144-6's MultiVolt I/O on the 144-pin LFQFP package supports direct 3.3V and 5.0V interfacing without external level shifters, simplifying designs that must bridge modern 3.3V ASICs to legacy 5V peripherals. Its 112 I/Os accept TTL/CMOS thresholds on a per-pin basis via VCCIO banks, allowing mixed-voltage signals on the same device. The 672-cell capacity handles UARTs, FIFOs, and parallel-port glue logic in a single chip. In-circuit reconfigurability (ICR) lets designers iterate on protocol logic without board changes. For new designs targeting 3.3V-only systems, migrate to a Cyclone III or later FPGA with similar density at lower power.
Recommended
State-Machine Replacement in Embedded Controllers
The EPF8820ATC144-6's 672 logic cells and 8K usable gates are ideal for implementing complex state machines that would otherwise require multiple PAL/GAL devices. Each Logic Element includes a 4-input LUT, register, and carry chain, supporting Moore and Mealy state machines with up to hundreds of states. The 125MHz internal frequency allows state-machine operation well above typical microcontrollers, and the 144-pin LFQFP exposes enough I/O for 32-bit datapath glue plus dedicated inputs. JTAG-based configuration and in-system reconfigurability let engineers iterate on state-machine logic during development. The -6 speed grade is acceptable for state machines with sub-50MHz clock rates.
Recommended
VME Bus Interface in Legacy Industrial Systems
The EPF8820ATC144-6 is well matched to VMEbus interface cards in legacy industrial and test-and-measurement equipment. Its 112 user I/Os comfortably handle the VME 32-bit address/data bus, arbitration lines, and interrupt request/acknowledge signals. MultiVolt I/O on the 144-pin package interfaces directly to 5V VME transceivers without external buffers. The 672-cell capacity accommodates full bus-master arbitration, address pipelining, and block-transfer handshaking in one device. SRAM configuration supports last-minute firmware updates in the field. For new VME64 designs, consider migrating to a larger FLEX 8000 device (EPF81188A or EPF81500A) with higher I/O count.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820ATC144-6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820ATC144-4N | EPF8820ATC144-4 | EPF8820ATC144-3N | EPF8820ATC144-3 | EPF8820ATC144-2N | EPF8820ATC144-2 |
|---|---|---|---|---|---|---|---|
| Package | 144-pin TQFP (LFQFP) | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Family | FLEX 8000 (EPF8820A) | FLEX 8000 (EPF8820A) | FLEX 8000 (EPF8820A) | FLEX 8000 (EPF8820A) | FLEX 8000 (EPF8820A) | FLEX 8000 (EPF8820A) | FLEX 8000 (EPF8820A) |
| Speed Grade | -6 (slowest) | -4 (faster) | -4 (faster) | -3 (faster) | -3 (faster) | -2 (fastest) | -2 (fastest) |
| Logic Cells | 672 | 672 | 672 | 672 | 672 | 672 | 672 |
| Usable Gates | ~8,000 | ~8,000 | ~8,000 | ~8,000 | ~8,000 | ~8,000 | ~8,000 |
| User I/Os | 112 | 112 | 112 | 112 | 112 | 112 | 112 |
| Supply Voltage | 5 V (MultiVolt I/O 3.3V/5.0V) | 5 V (MultiVolt I/O 3.3V/5.0V) | 5 V (MultiVolt I/O 3.3V/5.0V) | 5 V (MultiVolt I/O 3.3V/5.0V) | 5 V (MultiVolt I/O 3.3V/5.0V) | 5 V (MultiVolt I/O 3.3V/5.0V) | 5 V (MultiVolt I/O 3.3V/5.0V) |
| Configuration Mode | SRAM (in-system reconfigurable) | SRAM (in-system reconfigurable) | SRAM (in-system reconfigurable) | SRAM (in-system reconfigurable) | SRAM (in-system reconfigurable) | SRAM (in-system reconfigurable) | SRAM (in-system reconfigurable) |
Key Differentiators
- Lowest-cost EPF8820ATC144 speed grade (vs EPF8820ATC144-2)
- Identical 144-pin LFQFP pinout across the entire EPF8820ATC144 family (vs EPF8820ATC100-2)
- Legacy 5V MultiVolt I/O without external level shifters (vs EPF8452ALC84-4)
Design Notes
Separate VCCINT (5V core) and VCCIO (3.3V or 5.0V I/O bank supplies) with adequate decoupling - place 0.1uF ceramic capacitors near every VCCINT and VCCIO pin, plus bulk 10-47uF tantalum or ceramic at each supply rail. The MultiVolt I/O feature on 144-pin packages lets you mix 3.3V and 5.0V signaling on different banks without level shifters - consult the FLEX 8000 datasheet for the exact bank assignments.
Configuration data is volatile - SRAM-based FLEX 8000 devices must be configured at every power-up. Always include an Altera EPC1, EPC2, EPC1213, EPC1064, or EPC1441 serial configuration device (or equivalent parallel EPROM/controller) on the board. Failure to provide a configuration source leaves the device in undefined state with all I/Os tri-stated. For JTAG-based configuration, ensure TCK/TMS/TDI/TDO are properly pulled and the JTAG chain is correctly ordered with any other JTAG devices on the board.
The 144-pin TQFP (LFQFP) requires careful PCB layout with 0.5mm pitch traces. Use 4-layer board with continuous ground plane beneath the device for signal integrity and power distribution. Place configuration device (EPC1441) within 50mm of the FPGA to keep DCLK/Data traces short. Route JTAG signals to a header with the correct pinout for Altera ByteBlaster or USB-Blaster download cables.
MultiVolt I/O banks can mix 3.3V and 5.0V signals on the same device, but each bank's VCCIO must be tied to a single voltage. Do not mix voltages within one bank or you risk input-clamping currents and long-term reliability issues. For high-speed outputs (>50MHz), use 5V-tolerant receivers rated for the slower edge rates typical of 5V CMOS. For inputs from 3.3V devices into 5V VCCIO banks, ensure the 3.3V logic-high VIH is above the 5V bank's threshold.
FLEX 8000 devices use 5V core supply which generates substantial heat compared to modern 1.2V FPGAs. At full toggle activity across all 112 I/Os, expect junction temperature to rise significantly. Provide adequate copper pour around the 144-pin TQFP - at least 1 square inch of 2oz copper on top and bottom layers connected via thermal vias. For sealed enclosures or stacked boards, verify theta_JA against the FLEX 8000 datasheet and derate ambient temperature accordingly.
Compliance Information
EPF8820ATC144-6 is an obsolete Altera FLEX 8000 family FPGA. RoHS/REACH status not explicitly stated in the provided web data; marked unknown. AEC-Q100 not applicable (commercial temperature grade 0C to 70C). Lead-free per Altera FLEX 8000 family standard (post-2000 Altera products transitioned to lead-free).
