EPM3128ATC100-7 - MAX 3000A CPLD, 128 Macro Cells, 100-TQFP | Intel
MPN: EPM3128ATC100-7 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $15.1 | $15.10 |
| 10 | $13.8 | $138.00 |
| 100 | $11.95 | $1,195.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.2 | $9,200.00 |
Drop-in alternatives for EPM3128ATC100-7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM3128ATC100-7N
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View Datasheet βEPM3128ATC100-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Typical Gates | 2500 |
| User I/Os | 80 |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | 7.5 ns |
| Counter Frequency (fCNT) | 129.9 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| I/O Voltage Tolerance | 5.0 V tolerant inputs |
| Programming Technology | EEPROM (non-volatile, in-system programmable) |
| ISP Standard | IEEE Std. 1532 (JTAG) |
| Package | 100-pin TQFP, 14x14 mm, 0.5 mm pitch |
| Operating Temperature | 0C to +70C (Commercial) |
| Speed Grade | -7 (fastest grade in family) |
| Process Technology | CMOS EEPROM |
EPM3128ATC100-7 Pin Configuration
| Pin 1 | I/O β General-purpose I/O (bank 1) |
| Pin 2 | I/O β General-purpose I/O (bank 1) |
| Pin 3 | I/O β General-purpose I/O (bank 1) |
| Pin 4 | I/O β General-purpose I/O (bank 1) |
| Pin 5 | I/O β General-purpose I/O (bank 1) |
| Pin 6 | I/O β General-purpose I/O (bank 1) |
| Pin 7 | I/O β General-purpose I/O (bank 1) |
| Pin 8 | I/O β General-purpose I/O (bank 1) |
| Pin 9 | VCCINT β 3.3 V core power |
| Pin 10 | I/O β General-purpose I/O (bank 1) |
| Pin 11 | I/O β General-purpose I/O (bank 1) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β General-purpose I/O (bank 2) |
| Pin 14 | I/O β General-purpose I/O (bank 2) |
| Pin 15 | I/O β General-purpose I/O (bank 2) |
| Pin 16 | I/O β General-purpose I/O (bank 2) |
| Pin 17 | I/O β General-purpose I/O (bank 2) |
| Pin 18 | I/O β General-purpose I/O (bank 2) |
| Pin 19 | I/O β General-purpose I/O (bank 2) |
| Pin 20 | I/O β General-purpose I/O (bank 2) |
| Pin 21 | I/O β General-purpose I/O (bank 2) |
| Pin 22 | I/O β General-purpose I/O (bank 2) |
| Pin 23 | GND β Ground |
| Pin 24 | I/O β General-purpose I/O (bank 2) |
| Pin 25 | I/O β General-purpose I/O (bank 2) |
| Pin 26 | I/O β General-purpose I/O (bank 2) |
| Pin 27 | I/O β General-purpose I/O (bank 2) |
| Pin 28 | I/O β General-purpose I/O (bank 2) |
| Pin 29 | I/O β General-purpose I/O (bank 2) |
| Pin 30 | I/O β General-purpose I/O (bank 2) |
| Pin 31 | I/O β General-purpose I/O (bank 2) |
| Pin 32 | VCCINT β 3.3 V core power |
| Pin 33 | I/O β General-purpose I/O (bank 2) |
| Pin 34 | I/O β General-purpose I/O (bank 2) |
| Pin 35 | I/O β General-purpose I/O (bank 2) |
| Pin 36 | I/O β General-purpose I/O (bank 2) |
| Pin 37 | GND β Ground |
| Pin 38 | TDI β JTAG Test Data In (IEEE 1532) |
| Pin 39 | TMS β JTAG Test Mode Select (IEEE 1532) |
| Pin 40 | TCK β JTAG Test Clock (IEEE 1532) |
| Pin 41 | I/O β General-purpose I/O (bank 3) |
| Pin 42 | I/O β General-purpose I/O (bank 3) |
| Pin 43 | I/O β General-purpose I/O (bank 3) |
| Pin 44 | I/O β General-purpose I/O (bank 3) |
| Pin 45 | I/O β General-purpose I/O (bank 3) |
| Pin 46 | I/O β General-purpose I/O (bank 3) |
| Pin 47 | I/O β General-purpose I/O (bank 3) |
| Pin 48 | I/O β General-purpose I/O (bank 3) |
| Pin 49 | I/O β General-purpose I/O (bank 3) |
| Pin 50 | VCCINT β 3.3 V core power |
| Pin 51 | I/O β General-purpose I/O (bank 3) |
| Pin 52 | I/O β General-purpose I/O (bank 3) |
| Pin 53 | GND β Ground |
| Pin 54 | I/O β General-purpose I/O (bank 3) |
| Pin 55 | I/O β General-purpose I/O (bank 3) |
| Pin 56 | I/O β General-purpose I/O (bank 3) |
| Pin 57 | I/O β General-purpose I/O (bank 3) |
| Pin 58 | I/O β General-purpose I/O (bank 3) |
| Pin 59 | I/O β General-purpose I/O (bank 3) |
| Pin 60 | I/O β General-purpose I/O (bank 3) |
| Pin 61 | I/O β General-purpose I/O (bank 3) |
| Pin 62 | I/O β General-purpose I/O (bank 3) |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β General-purpose I/O (bank 4) |
| Pin 65 | I/O β General-purpose I/O (bank 4) |
| Pin 66 | I/O β General-purpose I/O (bank 4) |
| Pin 67 | I/O β General-purpose I/O (bank 4) |
| Pin 68 | I/O β General-purpose I/O (bank 4) |
| Pin 69 | I/O β General-purpose I/O (bank 4) |
| Pin 70 | I/O β General-purpose I/O (bank 4) |
| Pin 71 | I/O β General-purpose I/O (bank 4) |
| Pin 72 | VCCINT β 3.3 V core power |
| Pin 73 | I/O β General-purpose I/O (bank 4) |
| Pin 74 | I/O β General-purpose I/O (bank 4) |
| Pin 75 | I/O β General-purpose I/O (bank 4) |
| Pin 76 | I/O β General-purpose I/O (bank 4) |
| Pin 77 | I/O β General-purpose I/O (bank 4) |
| Pin 78 | I/O β General-purpose I/O (bank 4) |
| Pin 79 | I/O β General-purpose I/O (bank 4) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β General-purpose I/O (bank 4) |
| Pin 82 | I/O β General-purpose I/O (bank 4) |
| Pin 83 | I/O β General-purpose I/O (bank 1) |
| Pin 84 | I/O β General-purpose I/O (bank 1) |
| Pin 85 | I/O β General-purpose I/O (bank 1) |
| Pin 86 | I/O β General-purpose I/O (bank 1) |
| Pin 87 | I/O β General-purpose I/O (bank 1) |
| Pin 88 | I/O β General-purpose I/O (bank 1) |
| Pin 89 | I/O β General-purpose I/O (bank 1) |
| Pin 90 | I/O β General-purpose I/O (bank 1) |
| Pin 91 | I/O β General-purpose I/O (bank 1) |
| Pin 92 | I/O β General-purpose I/O (bank 1) |
| Pin 93 | GND β Ground |
| Pin 94 | I/O β General-purpose I/O (bank 1) |
| Pin 95 | I/O β General-purpose I/O (bank 1) |
| Pin 96 | I/O β General-purpose I/O (bank 1) |
| Pin 97 | I/O β General-purpose I/O (bank 1) |
| Pin 98 | TDO β JTAG Test Data Out (IEEE 1532) |
| Pin 99 | I/O β General-purpose I/O (bank 1) |
| Pin 100 | I/O β General-purpose I/O (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC100-7 is suitable for 7 applications: Legacy 80-Series Bus Decoding and Address Latch Generation, Industrial Control Board Glue Logic, 5 V to 3.3 V Voltage Translation with Handshaking, Board-Test Multiplexer and JTAG Controller, State-Machine and Sequencing Controller, Legacy Interface Bridging (ISA, VME, PC/104), Display and LED Multiplex Driver.
Legacy 80-Series Bus Decoding and Address Latch Generation
The EPM3128ATC100-7's 128 macro cells and 80 user I/Os make it well suited for decoding 16- and 24-bit address buses and generating address-latch enable (ALE) strobes for 80C186, 8051, and 80186 microprocessor glue logic. With 7.5 ns tPD the device comfortably meets the 8 ns cycle time of these microcontrollers, and the 5.0 V tolerant inputs allow direct connection to 5 V processor buses without level shifters. Typical reference designs use four LABs configured as a primary decoder plus three secondary enable generators, with one LAB reserved for handshake and wait-state logic. Compared with discrete 74HC logic, the EPM3128ATC100-7 replaces 8-12 packages with one IC, saving board area and reducing BOM count.
Recommended
Industrial Control Board Glue Logic
In PLC, motor-drive, and process-control boards the EPM3128ATC100-7 acts as the deterministic glue between the microcontroller, ADC/DAC chips, and isolation barriers. Its 7.5 ns tPD is consistent across temperature, which is critical for industrial feedback loops that cannot tolerate FPGA-style delay variation. The non-volatile EEPROM cell means the board boots into the correct state on power-up without a configuration flash, eliminating a common PLC failure mode. Designers typically allocate one LAB for encoder quadrature decoding, one LAB for PWM signal generation, and one LAB for fault-handling state machines, leaving one LAB for board-test JTAG access via the IEEE 1532 ISP interface.
Recommended
5 V to 3.3 V Voltage Translation with Handshaking
The EPM3128ATC100-7's 5.0 V tolerant inputs allow direct interfacing with 5 V microcontrollers and peripherals, while its 3.3 V LVTTL outputs cleanly drive 3.3 V ASICs, FPGAs, and memory. The device can implement direction-aware translators with ready/acknowledge handshaking in a single LAB, replacing discrete 74LVC4245A buffers and saving PCB area. The 7.5 ns tPD adds minimal latency to the translation path, so handshake signals remain deterministic. This is a common pattern in mixed-voltage industrial and instrumentation boards where one rail must remain at 5 V for legacy analog components while the digital core migrates to 3.3 V.
Recommended
Board-Test Multiplexer and JTAG Controller
The EPM3128ATC100-7's integrated IEEE Std. 1532 ISP interface plus its 80 I/Os are well matched to board-test multiplexer designs that route JTAG chains from multiple ICs to a single test header. Each I/O can be configured as a tri-state buffer, allowing the CPLD to isolate the boundary-scan chain of each downstream IC during production test. The non-volatile configuration means the test mode is permanent until reprogrammed, eliminating the need for a separate test-mode jumper. The 7.5 ns tPD ensures the JTAG TCK-to-TDO round-trip is fast enough to remain transparent to boundary-scan timing requirements.
Recommended
State-Machine and Sequencing Controller
With 128 macro cells the EPM3128ATC100-7 can implement complex multi-state sequencing machines that would otherwise require 4-6 PAL/GAL devices. Typical applications include power-supply sequencing (rail-by-rail enable with programmable delays), reset distribution in multi-IC systems, and protocol converters (UART-to-SPI, I2C-to-parallel). The deterministic 7.5 ns tPD guarantees that sequencing events happen in a known order even at high clock rates, which is essential for power-rail ramp sequencing in systems with strict power-good requirements. The EEPROM-based configuration is retained through power cycles without an external boot memory.
Recommended
Legacy Interface Bridging (ISA, VME, PC/104)
The EPM3128ATC100-7 is widely deployed as a bridge between modern microcontrollers and legacy parallel buses such as ISA, VME, and PC/104, where 80 user I/Os and 7.5 ns tPD cleanly map 16-bit data plus 24-bit address plus chip-select signals. The 5.0 V tolerant inputs directly accept 5 V ISA bus levels, and the 3.3 V LVCMOS outputs connect cleanly to modern 3.3 V SoCs. One LAB can implement the full ISA bus decoder (I/O read, I/O write, memory read, memory write, address latch enable), while a second LAB handles wait-state insertion and bus arbitration. This bridges 1980s-era peripheral cards to 2020s-era processors without redesigning the legacy interface.
Recommended
Display and LED Multiplex Driver
The EPM3128ATC100-7's 80 I/Os can drive a 7-segment or 14-segment multiplexed display with column and row decoding in a single device, replacing 6-8 discrete 74HC138 / 74HC595 chains. At 129.9 MHz fCNT the device can refresh a 16-digit display at 1 kHz per digit with comfortable margin. The non-volatile configuration means the display pattern is retained through power cycles, and the 5 V tolerant inputs allow direct connection to 5 V keypad scan matrices. Designers commonly use one LAB for the multiplexer address counter, one LAB for character ROM lookup, and two LABs for PWM intensity control.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC100-7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC100-7N | EPM3128ATC100-10N | EPM3128ATC100-10 | EPM3128ATC100-5N | EPM3128ATC100-5 | EPM3128ATC100-10NS |
|---|---|---|---|---|---|---|---|
| Package | TQFP-100 (14x14 mm) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns | 10 ns | 10 ns | 5 ns | 5 ns | 10 ns |
| Counter Frequency (fCNT) | 129.9 MHz | 129.9 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 80 | 80 | 80 | 80 | 80 | 80 | 80 |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Lead-Free Finish | Unknown (legacy part) | Yes (N suffix) | Yes (N suffix) | No (legacy Pb) | Yes (N suffix) | No (legacy Pb) | Yes (N suffix) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest -7 speed grade in the EPM3128 family delivers 7.5 ns tPD and 129.9 MHz fCNT (vs EPM3128ATC100-10N)
- Identical silicon to the lead-free EPM3128ATC100-7N, allowing easy migration to RoHS-compliant builds (vs EPM3128ATC100-7N)
- Two-fold logic capacity vs the EPM3064ATC100-7 in the same TQFP-100 package (vs EPM3064ATC100-7)
- Non-volatile EEPROM configuration eliminates external boot memory and SRAM-FPGA inrush issues (vs EPM240T100C5N (MAX II, SRAM-based))
Design Notes
The EPM3128ATC100-7 requires four VCCINT pins (9, 32, 50, 72) and four GND pins (12, 23, 37, 53) to be connected on the PCB, plus two additional GND pins (63, 80, 93) per the TQFP-100 layout. Per the MAX 3000A datasheet, place one 0.1 uF decoupling capacitor within 100 mils of every VCCINT pin and one bulk 10 uF tantalum or ceramic at the package entry point. The ICCINT supply must be monotonic and rise to 3.3 V within 100 ms to ensure proper ISP configuration; a soft-start RC ramp is acceptable if the rise time stays within this window.
The 100-pin TQFP has 0.5 mm lead pitch and a 14x14 mm body; the recommended PCB land pattern uses 0.3 mm wide pads with 1.5 mm length, per IPC-7351 nominal density. Traces should escape on all four sides with vias-in-pad only if the PCB fab supports filled-and-capped vias; otherwise use via-at-pad-end with a 0.2 mm trace to the via barrel. Estimated: with 80 I/Os on a 4-layer 1 oz copper board, expect to route 4-6 mil traces between pads using a 1-2-1 via fanout; 8+ mil dielectric clearance is required between adjacent I/O traces to maintain 50 ohm controlled impedance.
A common pitfall when designing with the EPM3128ATC100-7 is leaving the JTAG pins (TCK pin 40, TMS pin 39, TDI pin 38, TDO pin 98) floating. Per IEEE Std. 1532 ISP requirements, TMS and TDI must be pulled up to VCCINT through 10 kΞ©ty resistors at the device pins (not at the connector) to prevent spurious JTAG state transitions during power-up. TDO is high-impedance and does not require a pull-up, but TCK should be pulled down to ground through 10 kΞ©ty to define the idle clock state. Without these pulls, in-system programming can fail intermittently and the device may appear corrupted.
Although the EPM3128ATC100-7 has 5.0 V tolerant inputs, the I/O output stage drives 3.3 V LVCMOS/LVTTL only. When interfacing with 5 V TTL receivers, ensure the Vih(min) of the receiver is below the CPLD's Voh(min) of 2.4 V at 4 mA. For 5 V CMOS receivers with Vih(min) of 3.5 V, external pull-ups to 5 V are required - this is documented in the MAX 3000A Family Data Sheet application notes section. Series resistors of 33 Ξ©ty on each output can dampen reflections on traces longer than 50 mm.
The EPM3128ATC100-7 commercial-temperature device is rated for 0C to 70C operation. In enclosed industrial enclosures, junction temperature can exceed 70C even at modest toggle rates because the TQFP-100 has no exposed thermal pad and relies on the PCB copper pour for heat dissipation. Estimated: at 50 percent toggle rate on 80 outputs, ICCINT is approximately 60 mA (1.98 W). With a 4-layer 1 oz copper PCB and no airflow, theta_JA is approximately 45 C/W, giving a junction-to-ambient rise of 89 C. Designers should either reduce toggle rate, derate to 50 percent output loading, or migrate to the industrial-temperature EPM3128ATI100-7N.
Compliance Information
Part is in the legacy MAX 3000A family; Intel/Altera RoHS and REACH compliance documentation not located in the verified web data. The EPM3128ATC100-7N variant carries a lead-free terminal finish (Pb-free matte Sn), but formal RoHS/REACH compliance status should be confirmed with the manufacturer's product page. Not AEC-Q100 qualified; the part is intended for commercial/industrial-grade designs.
