EPM7256SRC208-10 - MAX 7000S CPLD 256 Macrocell 10ns | Intel
MPN: EPM7256SRC208-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.25 | $382.50 |
| 100 | $34 | $3,400.00 |
| 500 | $30.6 | $15,300.00 |
| 1,000 | $27.2 | $27,200.00 |
Drop-in alternatives for EPM7256SRC208-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7256SQC208-10
✅ Drop-In✓ In Stock
$11.2 / Unit
View Datasheet →EPM7256SQC208-7
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View Datasheet →EPM7256SQC208-15
✅ Drop-In✓ In Stock
$3.65 / Unit
View Datasheet →EPM7256SQC208-15N
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View Datasheet →EPM7256SQC208-7N
✅ Drop-In✓ In Stock
$27.2 / Unit
View Datasheet →EPM7256SQI208-10
✅ Drop-In✓ In Stock
$0.4 / Unit
View Datasheet →EPM7256SRC208-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 256 |
| Number of Logic Array Blocks (LABs) | 16 |
| Number of Gates | 5000 |
| Number of User I/O Pins | 164 |
| Maximum Propagation Delay (tPD) | 10 ns |
| Maximum Operating Frequency | 100 MHz |
| Supply Voltage (Internal) | 4.75 V to 5.25 V |
| Programmable Type | In System Programmable (ISP, JTAG) |
| Configuration Technology | EEPROM |
| Package | 208-pin RQFP (BFQFP) exposed pad, 28x28 mm |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (TA, commercial) |
| Terminal Form | Gull Wing |
| Package Shape | Square |
| Product Status | Obsolete |
EPM7256SRC208-10 Pin Configuration
| Pin 1 | I/O — User I/O pin (per datasheet) |
| Pin 2 | I/O — User I/O pin (per datasheet) |
| Pin 3 | I/O — User I/O pin (per datasheet) |
| Pin 4 | I/O — User I/O pin (per datasheet) |
| Pin 5 | I/O — User I/O pin (per datasheet) |
| Pin 6 | I/O — User I/O pin (per datasheet) |
| Pin 7 | I/O — User I/O pin (per datasheet) |
| Pin 8 | I/O — User I/O pin (per datasheet) |
| Pin 9 | I/O — User I/O pin (per datasheet) |
| Pin 10 | I/O — User I/O pin (per datasheet) |
| Pin 11 | I/O — User I/O pin (per datasheet) |
| Pin 12 | I/O — User I/O pin (per datasheet) |
| Pin 13 | I/O — User I/O pin (per datasheet) |
| Pin 14 | I/O — User I/O pin (per datasheet) |
| Pin 15 | I/O — User I/O pin (per datasheet) |
| Pin 16 | I/O — User I/O pin (per datasheet) |
| Pin 17 | I/O — User I/O pin (per datasheet) |
| Pin 18 | I/O — User I/O pin (per datasheet) |
| Pin 19 | I/O — User I/O pin (per datasheet) |
| Pin 20 | I/O — User I/O pin (per datasheet) |
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| Pin 50 | I/O — User I/O pin (per datasheet) |
| Pin 51 | I/O — User I/O pin (per datasheet) |
| Pin 52 | I/O — User I/O pin (per datasheet) |
| Pin 53 | GND — Ground (per datasheet) |
| Pin 54 | VCC — 5 V supply (per datasheet) |
| Pin 55 | I/O — User I/O pin (per datasheet) |
| Pin 56 | I/O — User I/O pin (per datasheet) |
| Pin 57 | I/O — User I/O pin (per datasheet) |
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| Pin 103 | I/O — User I/O pin (per datasheet) |
| Pin 104 | I/O — User I/O pin (per datasheet) |
| Pin 105 | GND — Ground (per datasheet) |
| Pin 106 | VCC — 5 V supply (per datasheet) |
| Pin 107 | I/O — User I/O pin (per datasheet) |
| Pin 108 | I/O — User I/O pin (per datasheet) |
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| Pin 120 | I/O — User I/O pin (per datasheet) |
| Pin 121 | I/O — User I/O pin (per datasheet) |
| Pin 122 | I/O — User I/O pin (per datasheet) |
| Pin 123 | I/O — User I/O pin (per datasheet) |
| Pin 124 | I/O — User I/O pin (per datasheet) |
| Pin 125 | I/O — User I/O pin (per datasheet) |
| Pin 126 | I/O — User I/O pin (per datasheet) |
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| Pin 155 | I/O — User I/O pin (per datasheet) |
| Pin 156 | I/O — User I/O pin (per datasheet) |
| Pin 157 | GND — Ground (per datasheet) |
| Pin 158 | VCC — 5 V supply (per datasheet) |
| Pin 159 | I/O — User I/O pin (per datasheet) |
| Pin 160 | I/O — User I/O pin (per datasheet) |
| Pin 161 | I/O — User I/O pin (per datasheet) |
| Pin 162 | I/O — User I/O pin (per datasheet) |
| Pin 163 | I/O — User I/O pin (per datasheet) |
| Pin 164 | I/O — User I/O pin (per datasheet) |
| Pin 165 | I/O — User I/O pin (per datasheet) |
| Pin 166 | I/O — User I/O pin (per datasheet) |
| Pin 167 | I/O — User I/O pin (per datasheet) |
| Pin 168 | I/O — User I/O pin (per datasheet) |
| Pin 169 | I/O — User I/O pin (per datasheet) |
| Pin 170 | I/O — User I/O pin (per datasheet) |
| Pin 171 | I/O — User I/O pin (per datasheet) |
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| Pin 174 | I/O — User I/O pin (per datasheet) |
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| Pin 176 | I/O — User I/O pin (per datasheet) |
| Pin 177 | I/O — User I/O pin (per datasheet) |
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| Pin 189 | I/O — User I/O pin (per datasheet) |
| Pin 190 | I/O — User I/O pin (per datasheet) |
| Pin 191 | I/O — User I/O pin (per datasheet) |
| Pin 192 | I/O — User I/O pin (per datasheet) |
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| Pin 194 | I/O — User I/O pin (per datasheet) |
| Pin 195 | I/O — User I/O pin (per datasheet) |
| Pin 196 | I/O — User I/O pin (per datasheet) |
| Pin 197 | I/O — User I/O pin (per datasheet) |
| Pin 198 | I/O — User I/O pin (per datasheet) |
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| Pin 200 | I/O — User I/O pin (per datasheet) |
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| Pin 206 | I/O — User I/O pin (per datasheet) |
| Pin 207 | I/O — User I/O pin (per datasheet) |
| Pin 208 | I/O — User I/O pin (per datasheet) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7256SRC208-10 is suitable for 6 applications: PCI/ISA Bus Bridging, Industrial Control Glue Logic, Legacy System Maintenance and Repair, Address Decoding and Chip-Select Logic, State Machine Implementation, Prototyping and Educational Logic Design.
PCI/ISA Bus Bridging
The EPM7256SRC208-10 fits PCI and ISA bus-bridge designs because its 164 user I/O pins and 256 macrocells can absorb the address, data, and control glue logic that would otherwise require dozens of discrete 74-series packages. Its 10 ns pin-to-pin delay supports bus cycles in the tens-of-megahertz range, and the EEPROM configuration retains the bridge logic without an external configuration PROM. Placed between the host bus and a peripheral controller, the CPLD performs address decoding, wait-state generation, and interrupt steering. The trade-off is that the 5 V supply and 208-pin RQFP footprint are large by modern standards, and the device is obsolete, so this application is limited to legacy board maintenance rather than new designs.
Recommended
Industrial Control Glue Logic
In industrial controllers, the EPM7256SRC208-10 consolidates chip-select generation, address decoding, and handshake logic for multiple peripherals into one 256-macrocell device. Its 5,000 gates and 164 I/O pins allow a single CPLD to replace a board full of 74HC logic, reducing component count and improving reliability. The 4.75-5.25 V supply matches legacy 5 V sensors and actuators, and the 10 ns tPD gives deterministic timing for state machines. The EEPROM configuration survives power cycles without a battery or configuration flash. The main consideration is thermal: the 208-pin RQFP exposed pad must be soldered to a copper area to dissipate the CPLD's switching power, and the obsolete status means spare parts must be sourced from remaining stock.
Recommended
Legacy System Maintenance and Repair
The EPM7256SRC208-10 is widely used to keep legacy telecom, industrial, and test equipment running after the original manufacturer has discontinued support. Because the device is in-system programmable via JTAG, a failed CPLD can be replaced and reprogrammed in the field using the original JEDEC programming file, restoring the board without a full redesign. The 208-pin RQFP exposed-pad package matches the original footprint, so repair is a true drop-in operation. The key risk is counterfeit or re-marked parts from the secondary market, so buyers should source from authorized distributors and verify date codes. Where the exact part cannot be found, EPM7256SQC208-10 provides functional equivalence at the cost of a package change.
Recommended
Address Decoding and Chip-Select Logic
The EPM7256SRC208-10 excels at address decoding and chip-select generation because its macrocell architecture implements wide AND/OR product terms in a single 10 ns delay stage. A 256-macrocell device can decode dozens of memory-mapped peripherals simultaneously, each with its own chip-select and wait-state logic, replacing a cascade of 74-series decoders that would add propagation delay and board area. The 164 I/O pins allow direct connection to address, data, and control buses without external buffers. Designers should register critical chip-select outputs in the macrocell flip-flops to eliminate decode glitches, and should distribute VCC decoupling across all supply pins to control ground bounce during simultaneous output switching.
Recommended
State Machine Implementation
The EPM7256SRC208-10 implements complex finite-state machines with up to 256 registered macrocells, each containing a flip-flop and programmable product-term logic. Because the MAX 7000S interconnect array delivers fixed, predictable delays, state-machine timing is deterministic and does not depend on routing, unlike SRAM-based FPGAs. This makes the device suitable for protocol engines, sequencers, and control FSMs running at up to 100 MHz. The EEPROM configuration means the state machine is live immediately at power-up, with no configuration load time. Designers should register all state outputs and use the global clock and clear networks to minimize skew, and should keep the number of product terms per transition within the macrocell limit to avoid cascaded expansion delays.
Recommended
Prototyping and Educational Logic Design
The EPM7256SRC208-10 is a useful platform for teaching programmable-logic design because its 256 macrocells and 164 I/O pins are large enough for realistic projects while the MAX 7000S architecture remains simple enough to understand at the product-term level. Students can implement counters, decoders, and state machines in Quartus or MAX+PLUS II and program the device in-system over JTAG, observing results immediately. The 5 V supply and 5 V-tolerant I/O interface directly with breadboard logic and legacy test equipment. The main drawback is that the device is obsolete and the 208-pin RQFP package requires a fine-pitch soldering or socket solution, so educational programs should consider migrating to an active MAX II or MAX V device.
Recommended
Recommended Products Summary
Engineering reference data for EPM7256SRC208-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7256SQC208-10 | EPM7256SQC208-7 | EPM7256SQC208-15 | EPM7256SQI208-10 |
|---|---|---|---|---|---|
| Package | 208-pin RQFP (BFQFP) exposed pad | 208-pin PQFP | 208-pin PQFP | 208-pin PQFP | 208-pin PQFP |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Number of Macrocells | 256 | 256 | 256 | 256 | 256 |
| Number of User I/O | 164 | 164 | 164 | 164 | 164 |
| Maximum Propagation Delay (tPD) | 10 ns | 10 ns | 7.5 ns | 15 ns | 10 ns |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programmable Type | In System Programmable (JTAG) | In System Programmable (JTAG) | In System Programmable (JTAG) | In System Programmable (JTAG) | In System Programmable (JTAG) |
| Number of Gates | 5000 | 5000 | 5000 | 5000 | 5000 |
| Product Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- RQFP exposed-pad footprint (vs EPM7256SQC208-10)
- 10 ns speed grade balance (vs EPM7256SQC208-7)
- Commercial temperature grade (vs EPM7256SQI208-10)
Design Notes
Decouple every VCC pin of the EPM7256SRC208-10 with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus at least one 10 uF bulk capacitor per supply rail. The MAX 7000S family switches many outputs simultaneously, and inadequate decoupling causes ground bounce and false clocking. Estimated: with 164 I/O switching at 5 V into 50 pF loads at 50 MHz, transient supply current can exceed several hundred milliamps, so low-ESL ceramic capacitors and a solid ground plane are essential.
The 208-pin RQFP package has an exposed thermal pad that must be soldered to a copper area on the PCB. Estimated: at 5 V and 100 MHz with typical toggle rates, the device can dissipate 1-2 W; without a thermal pad connection the junction temperature may exceed the 0C to +70C commercial rating. Use a thermal via array under the pad and connect it to the ground plane. Confirm the actual power estimate with Intel's power calculator for the MAX 7000S family.
Route the JTAG signals (TCK, TMS, TDI, TDO) as short, controlled-impedance traces and keep them away from high-speed I/O to avoid corrupting in-system programming. Provide a 10-pin JTAG header with proper VCC and GND references. Because the EPM7256SRC208-10 is obsolete, also design a test point or header for the configuration file so that a replacement device can be reprogrammed in the field without desoldering.
Do not assume EPM7256SQC208-10 is a footprint drop-in for EPM7256SRC208-10. The SRC suffix denotes the 208-pin RQFP exposed-pad package while SQC denotes the 208-pin PQFP; the land patterns differ. Verify the package drawing before substituting. Also confirm the speed grade: a -15 part has 15 ns tPD versus 10 ns for the -10, which can break timing in existing designs.
Compliance Information
Compliance data was not present in the verified web data for EPM7256SRC208-10. The lead-free (N) suffix variants such as EPM7256SQC208-7N and EPM7256SQC208-15N indicate lead-free construction, but the base part's RoHS/REACH status must be confirmed with the manufacturer or distributor.
