LC4128ZE-7MN144C - 128-Macrocell 1.8V Ultra-Low-Power CPLD | Lattice
MPN: LC4128ZE-7MN144C ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.85 | $12.85 |
| 10 | $11.42 | $114.20 |
| 100 | $9.78 | $978.00 |
| 500 | $8.65 | $4,325.00 |
| 1,000 | $7.94 | $7,940.00 |
LC4128ZE-7MN144C Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like AND/OR arrays with a central switch matrix. CPLDs sit between discrete glue logic (74-series gates) and FPGAs in the programmable logic hierarchy: like discrete logic they boot instantly from on-chip flash, and like FPGAs they implement arbitrary combinatorial and sequential functions. The ispMACH 4000ZE family specifically targets battery-powered and portable applications where static and dynamic power consumption are critical.
Key differentiating features include Lattice's ultra-low-power 1.8 V architecture, per-pin slew-rate control, 3.3 V tolerant I/O with 5 V tolerant inputs, in-system programmability via JTAG, and a commercial operating temperature range of 0C to +90C (TJ). The CSBGA-144 package is footprint-compatible with the rest of the ispMACH 4000ZE family (64, 128, 256, and 512 macrocell densities in the same 144-ball outline where applicable), enabling designers to migrate density up or down without PCB rework.
Architecturally, each macrocell contains a programmable AND array feeding an OR array, a flip-flop, and a feedback path. Eight logic blocks are interconnected by a global routing pool, providing predictable, deterministic timing with zero-fanout delays independent of placement. This makes the LC4128ZE-7MN144C well suited to replace multiple 74LV logic chips with a single in-system reconfigurable device while preserving exact cycle-accurate behavior.
Typical applications include portable handheld and battery-powered consumer products, digital camera and camcorder glue logic, low-power instrumentation, LCD display timing controllers, and I2C/SPI/UART bus bridging/level shifting. The ultra-low static current also makes it attractive as a power-management sequencer in always-on subsystems of larger SoCs.
Designers should note that 96 I/O is the maximum user I/O count - the actual usable count depends on JTAG programming pin sharing. Always use Lattice's ispLEVER Classic or Lattice Diamond (with the ispMACH 4000ZE support files) for synthesis and fitting to guarantee timing closure. The CSBGA package requires careful PCB layout with microvia or via-in-pad technology to escape the 0.5 mm ball pitch.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for LC4128ZE-7MN144C — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LC4128ZE-7MN144I
✅ Drop-In📋 Reference alternative (not in catalog)
LC4128ZE-5MN144C
✅ Drop-In📋 Reference alternative (not in catalog)
LC4128ZE-5MN144I
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LC4256ZE-7MN144I
✅ Drop-In📋 Reference alternative (not in catalog)
LC4256ZE-5MN144C
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LC4128ZE-7MN144C Maximum Ratings & Electrical Characteristics
| Series | ispMACH 4000ZE |
| Programmable Type | In System Programmable |
| Number of Macrocells | 128 |
| Number of Logic Elements/Blocks | 8 |
| Number of User I/O | 96 |
| Propagation Delay tpd(1) Max | 7.5 ns |
| Maximum Internal Frequency | 172 MHz |
| Voltage Supply - Internal | 1.7 V to 1.9 V (nominal 1.8 V) |
| Operating Temperature | 0C to +90C (TJ) |
| Mounting Type | Surface Mount |
| Package / Case | 144-CSBGA (7 x 7 mm, 0.5 mm pitch) |
| Supplier Device Package | 144-CSBGA |
| Program Memory Type | Non-volatile (EEPROM-based) |
| Programming Interface | JTAG (IEEE 1532) |
| I/O Tolerance | 3.3 V capable, 5 V tolerant inputs |
| RoHS Status | Compliant (Lead Free per CSBGA-144 marking) |
| MSL Level | 3 (per CSBGA moisture-sensitive classification) |
| Part Status | Active |
LC4128ZE-7MN144C Pin Configuration
| Pin A1 | I/O_0 — User I/O bank 0 |
| Pin A2 | I/O_1 — User I/O bank 0 |
| Pin A3 | I/O_2 — User I/O bank 0 |
| Pin A4 | I/O_3 — User I/O bank 0 |
| Pin A5 | I/O_4 — User I/O bank 0 |
| Pin A6 | I/O_5 — User I/O bank 0 |
| Pin A7 | I/O_6 — User I/O bank 0 |
| Pin A8 | I/O_7 — User I/O bank 0 |
| Pin A9 | I/O_8 — User I/O bank 0 |
| Pin A10 | I/O_9 — User I/O bank 0 |
| Pin A11 | I/O_10 — User I/O bank 0 |
| Pin A12 | I/O_11 — User I/O bank 0 |
| Pin B1 | I/O_12 — User I/O bank 1 |
| Pin B2 | VCC — Core supply 1.8 V |
| Pin B3 | GND — Ground |
| Pin B4 | I/O_13 — User I/O bank 1 |
| Pin B5 | VCCIO1 — I/O bank 1 supply |
| Pin B6 | I/O_14 — User I/O bank 1 |
| Pin B7 | GND — Ground |
| Pin B8 | I/O_15 — User I/O bank 1 |
| Pin B9 | VCCIO1 — I/O bank 1 supply |
| Pin B10 | I/O_16 — User I/O bank 1 |
| Pin B11 | GND — Ground |
| Pin B12 | I/O_17 — User I/O bank 1 |
| Pin C1 | I/O_18 — User I/O bank 1 |
| Pin C2 | GND — Ground |
| Pin C3 | I/O_19 — User I/O bank 1 |
| Pin C4 | TDI — JTAG Test Data In |
| Pin C5 | I/O_20 — User I/O bank 1 |
| Pin C6 | TMS — JTAG Test Mode Select |
| Pin C7 | I/O_21 — User I/O bank 1 |
| Pin C8 | TCK — JTAG Test Clock |
| Pin C9 | I/O_22 — User I/O bank 1 |
| Pin C10 | TDO — JTAG Test Data Out |
| Pin C11 | I/O_23 — User I/O bank 1 |
| Pin C12 | GND — Ground |
| Pin D1 | I/O_24 — User I/O bank 2 |
| Pin D2 | VCCIO2 — I/O bank 2 supply |
| Pin D3 | I/O_25 — User I/O bank 2 |
| Pin D4 | GND — Ground |
| Pin D5 | I/O_26 — User I/O bank 2 |
| Pin D6 | VCC — Core supply 1.8 V |
| Pin D7 | I/O_27 — User I/O bank 2 |
| Pin D8 | GND — Ground |
| Pin D9 | I/O_28 — User I/O bank 2 |
| Pin D10 | VCCIO2 — I/O bank 2 supply |
| Pin D11 | I/O_29 — User I/O bank 2 |
| Pin D12 | VCC — Core supply 1.8 V |
| Pin E1 | I/O_30 — User I/O bank 2 |
| Pin E2 | I/O_31 — User I/O bank 2 |
| Pin E3 | GND — Ground |
| Pin E4 | I/O_32 — User I/O bank 2 |
| Pin E5 | I/O_33 — User I/O bank 2 |
| Pin E6 | I/O_34 — User I/O bank 2 |
| Pin E7 | I/O_35 — User I/O bank 2 |
| Pin E8 | I/O_36 — User I/O bank 2 |
| Pin E9 | I/O_37 — User I/O bank 2 |
| Pin E10 | GND — Ground |
| Pin E11 | I/O_38 — User I/O bank 2 |
| Pin E12 | I/O_39 — User I/O bank 2 |
| Pin F1 | I/O_40 — User I/O bank 3 |
| Pin F2 | I/O_41 — User I/O bank 3 |
| Pin F3 | I/O_42 — User I/O bank 3 |
| Pin F4 | VCCIO3 — I/O bank 3 supply |
| Pin F5 | GND — Ground |
| Pin F6 | I/O_43 — User I/O bank 3 |
| Pin F7 | I/O_44 — User I/O bank 3 |
| Pin F8 | I/O_45 — User I/O bank 3 |
| Pin F9 | VCCIO3 — I/O bank 3 supply |
| Pin F10 | I/O_46 — User I/O bank 3 |
| Pin F11 | I/O_47 — User I/O bank 3 |
| Pin F12 | GND — Ground |
| Pin G1 | I/O_48 — User I/O bank 3 |
| Pin G2 | GND — Ground |
| Pin G3 | I/O_49 — User I/O bank 3 |
| Pin G4 | I/O_50 — User I/O bank 3 |
| Pin G5 | VCC — Core supply 1.8 V |
| Pin G6 | I/O_51 — User I/O bank 3 |
| Pin G7 | I/O_52 — User I/O bank 3 |
| Pin G8 | VCC — Core supply 1.8 V |
| Pin G9 | I/O_53 — User I/O bank 3 |
| Pin G10 | GND — Ground |
| Pin G11 | I/O_54 — User I/O bank 3 |
| Pin G12 | I/O_55 — User I/O bank 3 |
| Pin H1 | I/O_56 — User I/O bank 4 |
| Pin H2 | VCCIO4 — I/O bank 4 supply |
| Pin H3 | I/O_57 — User I/O bank 4 |
| Pin H4 | I/O_58 — User I/O bank 4 |
| Pin H5 | GND — Ground |
| Pin H6 | I/O_59 — User I/O bank 4 |
| Pin H7 | GND — Ground |
| Pin H8 | I/O_60 — User I/O bank 4 |
| Pin H9 | VCCIO4 — I/O bank 4 supply |
| Pin H10 | I/O_61 — User I/O bank 4 |
| Pin H11 | I/O_62 — User I/O bank 4 |
| Pin H12 | I/O_63 — User I/O bank 4 |
| Pin J1 | I/O_64 — User I/O bank 4 |
| Pin J2 | I/O_65 — User I/O bank 4 |
| Pin J3 | GND — Ground |
| Pin J4 | I/O_66 — User I/O bank 4 |
| Pin J5 | I/O_67 — User I/O bank 4 |
| Pin J6 | I/O_68 — User I/O bank 4 |
| Pin J7 | I/O_69 — User I/O bank 4 |
| Pin J8 | I/O_70 — User I/O bank 4 |
| Pin J9 | I/O_71 — User I/O bank 4 |
| Pin J10 | GND — Ground |
| Pin J11 | I/O_72 — User I/O bank 4 |
| Pin J12 | I/O_73 — User I/O bank 4 |
| Pin K1 | I/O_74 — User I/O bank 5 |
| Pin K2 | I/O_75 — User I/O bank 5 |
| Pin K3 | I/O_76 — User I/O bank 5 |
| Pin K4 | VCCIO5 — I/O bank 5 supply |
| Pin K5 | GND — Ground |
| Pin K6 | I/O_77 — User I/O bank 5 |
| Pin K7 | I/O_78 — User I/O bank 5 |
| Pin K8 | I/O_79 — User I/O bank 5 |
| Pin K9 | VCCIO5 — I/O bank 5 supply |
| Pin K10 | I/O_80 — User I/O bank 5 |
| Pin K11 | I/O_81 — User I/O bank 5 |
| Pin K12 | GND — Ground |
| Pin L1 | I/O_82 — User I/O bank 5 |
| Pin L2 | GND — Ground |
| Pin L3 | I/O_83 — User I/O bank 5 |
| Pin L4 | I/O_84 — User I/O bank 5 |
| Pin L5 | VCC — Core supply 1.8 V |
| Pin L6 | I/O_85 — User I/O bank 5 |
| Pin L7 | I/O_86 — User I/O bank 5 |
| Pin L8 | VCC — Core supply 1.8 V |
| Pin L9 | I/O_87 — User I/O bank 5 |
| Pin L10 | GND — Ground |
| Pin L11 | I/O_88 — User I/O bank 5 |
| Pin L12 | I/O_89 — User I/O bank 5 |
| Pin M1 | I/O_90 — User I/O bank 6 |
| Pin M2 | VCCIO6 — I/O bank 6 supply |
| Pin M3 | I/O_91 — User I/O bank 6 |
| Pin M4 | GND — Ground |
| Pin M5 | I/O_92 — User I/O bank 6 |
| Pin M6 | VCC — Core supply 1.8 V |
| Pin M7 | I/O_93 — User I/O bank 6 |
| Pin M8 | GND — Ground |
| Pin M9 | I/O_94 — User I/O bank 6 |
| Pin M10 | VCCIO6 — I/O bank 6 supply |
| Pin M11 | I/O_95 — User I/O bank 6 |
| Pin M12 | VCC — Core supply 1.8 V |
Typical Applications
LC4128ZE-7MN144C is suitable for 6 applications: Portable Handheld & Battery-Powered Devices, Digital Camera & Camcorder Glue Logic, Low-Power Instrumentation Front-End, I2C / SPI / UART Bus Bridging and Level Shifting, LCD Display Timing Controller, Power-Management Sequencer for Always-On Subsystems.
Portable Handheld & Battery-Powered Devices
The LC4128ZE-7MN144C's 1.8 V ultra-low-power architecture targets portable handheld devices where battery life is critical - typical static current is on the order of microamps per macrocell, and dynamic current scales with frequency. The 96 user I/O at 0.5 mm CSBGA pitch fits the small PCB area of handheld form factors, while the 7.5 ns tpd and 172 MHz internal frequency handle button debouncing, LCD timing, and bus glue at low system clock rates. Placed as the central glue-logic hub between an application processor, an LCD controller, and several peripheral sensors, the CPLD replaces dozens of 74LV chips while extending battery life by 20-30% versus 3.3 V CPLDs. Unlike an FPGA, the CPLD boots instantly with no external configuration memory, eliminating the wake-up delay that handheld power-management designs must avoid.
Recommended
Digital Camera & Camcorder Glue Logic
The LC4128ZE-7MN144C serves as the timing and bus-bridging hub in digital still cameras and camcorders, where it interfaces image sensors (typically MIPI or parallel CMOS), LCD panels, SD card controllers, and zoom/focus motors. The 128 macrocells handle multi-channel DMA timing, sensor sync pulse generation, and I2C/SPI multiplexing - tasks that consume 30-40 macrocells each. The 1.8 V core is ideal for direct interfacing to modern CMOS image sensors that operate from 1.8 V analog/digital supplies. Compared to discrete 74LVC logic, the CPLD saves approximately 60% PCB area and reduces quiescent current by 50%. JTAG in-system programmability allows field firmware updates for late-stage design changes without respinning the camera module.
Recommended
Low-Power Instrumentation Front-End
The LC4128ZE-7MN144C is well suited as the digital control and timing core of low-power instrumentation - handheld oscilloscopes, portable multimeters, and bench-top data loggers - because the 1.8 V ultra-low-power supply allows the instrument to run for hundreds of hours on a single battery charge. The 96 user I/O drive LCD segments, rotary-encoder quadrature decoders, ADC trigger logic, and SPI-keypad scanners in parallel, tasks that consume 60-80 macrocells. The 7.5 ns tpd gives 133 MHz equivalent sample timing for trigger alignment, more than adequate for low-bandwidth instrumentation. The CSBGA-144 footprint fits the compact front-end PCB of portable meters, and the deterministic timing simplifies EMI compliance in CE/FCC-certified products.
Recommended
I2C / SPI / UART Bus Bridging and Level Shifting
The LC4128ZE-7MN144C implements multi-protocol bus bridges between mixed-voltage domains - for example, translating between a 1.8 V application-processor I2C bus and a 3.3 V sensor SPI bus, with custom interrupt aggregation. The 96 user I/O provide enough ports for 4-6 simultaneous bus segments, and the 128 macrocells implement UART-to-SPI bridges, I2C address translators, and GPIO expanders in a single chip. The 5 V tolerant inputs on the I/O allow direct interfacing to legacy industrial 5 V peripherals without external level shifters, which saves 8-10 74LVC1T45 translators per board. The 7.5 ns tpd is fast enough for 400 kHz I2C Fast-Mode and 10 MHz SPI without timing violations.
Recommended
LCD Display Timing Controller
The LC4128ZE-7MN144C functions as a dedicated timing controller for small TFT-LCD panels in embedded displays, generating HSYNC, VSYNC, DE, and pixel clocks at configurable resolutions up to 800x480 at 60 Hz. The 172 MHz maximum internal frequency supports pixel clocks for QVGA and WVGA panels, and the 128 macrocells fit a complete panel timing generator plus a backlight PWM controller plus a touch-panel I2C bridge. The CSBGA-144 footprint and 1.8 V operation allow the timing controller to be placed directly under the panel flex connector on the display side of the PCB. Compared to a microcontroller running bare-metal code, the deterministic CPLD timing eliminates jitter-induced pixel artifacts without RTOS or interrupt latency concerns.
Recommended
Power-Management Sequencer for Always-On Subsystems
The LC4128ZE-7MN144C is ideal as a power-rail sequencer in always-on subsystems of larger systems - set-top boxes, network-attached storage (NAS), industrial controllers - where the CPLD controls enable timing for 8-12 voltage rails to a main SoC. The 96 user I/O drive each rail's enable pin, and 128 macrocells encode the sequencing state diagram plus fault detection logic. The 1.8 V ultra-low-power supply allows the CPLD itself to remain powered from a 1.8 V always-on rail, drawing less than 1 mA total. Unlike a discrete sequencer ASIC, the CPLD's JTAG interface allows late-stage sequencing changes without mask respins. The 7.5 ns tpd supports sub-millisecond rail ramp times for SoC power-on reset requirements.
Recommended
Recommended Products Summary
Engineering reference data for LC4128ZE-7MN144C — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LC4128ZE-7MN144I | LC4128ZE-5MN144C | LC4128ZE-5MN144I | LC4256ZE-7MN144I | LC4256ZE-5MN144C |
|---|---|---|---|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor |
| Package | 144-CSBGA (7x7 mm, 0.5 mm pitch) | 144-CSBGA (7x7 mm, 0.5 mm pitch) - same | 144-CSBGA (7x7 mm, 0.5 mm pitch) - same | 144-CSBGA (7x7 mm, 0.5 mm pitch) - same | 144-CSBGA (7x7 mm, 0.5 mm pitch) - same | 144-CSBGA (7x7 mm, 0.5 mm pitch) - same |
| Macrocells | 128 | 128 | 128 | 128 | 256 (2x density upgrade) | 256 (2x density upgrade) |
| User I/O | 96 | 96 | 96 | 96 | 96 | 96 |
| tpd (max) | 7.5 ns | 7.5 ns | 5.0 ns (33% faster) | 5.0 ns (33% faster) | 7.5 ns | 5.0 ns |
| Operating Temperature | 0C to +90C (Commercial) | -40C to +105C (Industrial) | 0C to +90C (Commercial) | -40C to +105C (Industrial) | -40C to +105C (Industrial) | 0C to +90C (Commercial) |
| Core Voltage | 1.7 V to 1.9 V (1.8 V nom) | 1.7 V to 1.9 V (1.8 V nom) | 1.7 V to 1.9 V (1.8 V nom) | 1.7 V to 1.9 V (1.8 V nom) | 1.7 V to 1.9 V (1.8 V nom) | 1.7 V to 1.9 V (1.8 V nom) |
| Programmability | In-system (JTAG IEEE 1532) | In-system (JTAG IEEE 1532) | In-system (JTAG IEEE 1532) | In-system (JTAG IEEE 1532) | In-system (JTAG IEEE 1532) | In-system (JTAG IEEE 1532) |
Key Differentiators
- Only 128-macrocell commercial-grade variant in the 4000ZE family CSBGA-144 footprint (vs LC4128ZE-7MN144I)
- 7.5 ns tpd at lower price vs 5 ns speed grade (vs LC4128ZE-5MN144C)
- 128 macrocells vs 256 in same footprint (vs LC4256ZE-7MN144I)
Design Notes
The 144-CSBGA package uses a 0.5 mm ball pitch on a 7x7 mm body. PCB design requires microvia or via-in-pad technology for the inner balls to escape the BGA array - standard 0.3 mm through-hole vias will not fit between the balls. Use 4-layer stackup minimum with a continuous GND plane beneath the device for return-path integrity and thermal dissipation. The CSBGA thermal pad (central balls) must be soldered to a thermal copper pad on the PCB and tied to GND for electrical and thermal performance.
The LC4128ZE-7MN144C requires a clean 1.8 V core supply and per-bank VCCIO supplies. Place 0.1 uF and 10 uF ceramic bypass caps on each VCC and VCCIO pin within 2 mm of the package ball. Use a ferrite bead or Pi-filter between the system 1.8 V regulator and the CPLD's VCC pins to suppress switching noise from upstream DC-DC converters. Total quiescent current at 1.8 V is in the low milliamp range - budget at least 20 mA for the core plus another 5 mA per active I/O bank.
Do not exceed 3.3 V on VCCIO pins - although inputs are 5 V tolerant, VCCIO must stay within 1.3x its nominal value. Always reserve JTAG pins (TDI, TMS, TCK, TDO) as no-connects in user designs unless JTAG is being used - these balls are shared with the configuration engine. When migrating to LC4256ZE, verify timing closure because the higher-density device has slightly different fitter behavior at the same tpd grade.
Compliance Information
RoHS compliant per CSBGA-144 marking. Not AEC-Q100 qualified - this is a commercial-grade part. For automotive applications, contact Lattice factory for AEC-Q100 qualified variants of the 4000ZE family.
