XC3090L-8PC84I - XC3000 FPGA 6K Gates 320 Cells 80MHz | Xilinx
MPN: XC3090L-8PC84I ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85 | $850.00 |
| 100 | $72 | $7,200.00 |
| 500 | $62 | $31,000.00 |
| 1,000 | $55 | $55,000.00 |
Drop-in alternatives for XC3090L-8PC84I — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
XC3090L-8PC84C
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View Datasheet →XC3090L-125PC84C
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View Datasheet →XC3090L-8PC84BKJ
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View Datasheet →XC3090L-8PC84I Maximum Ratings & Electrical Characteristics
| Family | XC3000 Series FPGA |
| Gates | 6,000 usable gates |
| Configurable Logic Blocks (CLBs) | 320 |
| Configuration Program Store | 64,160 bits |
| User I/O | 70 |
| Maximum Toggle Frequency | 80 MHz |
| Core Supply Voltage | 3.3 V |
| Operating Temperature Grade | Industrial (-40 °C to +85 °C) |
| Package | 84-pin PLCC (J-Lead), QCCJ |
| Mounting Type | Surface Mount (J-Lead) |
| I/O Standard Support | TTL and CMOS (programmable per IOB) |
| Configuration Method | SRAM, loaded from external PROM or microprocessor |
| Process Technology | CMOS, SRAM-based |
XC3090L-8PC84I Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | I/O — User I/O pin (PA0) |
| Pin 3 | I/O — User I/O pin (PA1) |
| Pin 4 | I/O — User I/O pin (PA2) |
| Pin 5 | I/O — User I/O pin (PA3) |
| Pin 6 | I/O — User I/O pin (PA4) |
| Pin 7 | I/O — User I/O pin (PA5) |
| Pin 8 | I/O — User I/O pin (PA6) |
| Pin 9 | I/O — User I/O pin (PA7) |
| Pin 10 | I/O — User I/O pin (PB0) |
| Pin 11 | I/O — User I/O pin (PB1) |
| Pin 12 | VCC — 3.3 V core supply |
| Pin 13 | I/O — User I/O pin (PB2) |
| Pin 14 | I/O — User I/O pin (PB3) |
| Pin 15 | I/O — User I/O pin (PB4) |
| Pin 16 | I/O — User I/O pin (PB5) |
| Pin 17 | I/O — User I/O pin (PB6) |
| Pin 18 | I/O — User I/O pin (PB7) |
| Pin 19 | I/O — User I/O pin (PC0) |
| Pin 20 | I/O — User I/O pin (PC1) |
| Pin 21 | I/O — User I/O pin (PC2) |
| Pin 22 | I/O — User I/O pin (PC3) |
| Pin 23 | I/O — User I/O pin (PC4) |
| Pin 24 | I/O — User I/O pin (PC5) |
| Pin 25 | I/O — User I/O pin (PC6) |
| Pin 26 | I/O — User I/O pin (PC7) |
| Pin 27 | GND — Ground reference |
| Pin 28 | I/O — User I/O pin (PD0) |
| Pin 29 | I/O — User I/O pin (PD1) |
| Pin 30 | I/O — User I/O pin (PD2) |
| Pin 31 | I/O — User I/O pin (PD3) |
| Pin 32 | I/O — User I/O pin (PD4) |
| Pin 33 | I/O — User I/O pin (PD5) |
| Pin 34 | I/O — User I/O pin (PD6) |
| Pin 35 | I/O — User I/O pin (PD7) |
| Pin 36 | I/O — User I/O pin (PE0) |
| Pin 37 | I/O — User I/O pin (PE1) |
| Pin 38 | VCC — 3.3 V core supply |
| Pin 39 | I/O — User I/O pin (PE2) |
| Pin 40 | I/O — User I/O pin (PE3) |
| Pin 41 | I/O — User I/O pin (PE4) |
| Pin 42 | I/O — User I/O pin (PE5) |
| Pin 43 | I/O — User I/O pin (PE6) |
| Pin 44 | I/O — User I/O pin (PE7) |
| Pin 45 | I/O — User I/O pin (PF0) |
| Pin 46 | I/O — User I/O pin (PF1) |
| Pin 47 | I/O — User I/O pin (PF2) |
| Pin 48 | I/O — User I/O pin (PF3) |
| Pin 49 | I/O — User I/O pin (PF4) |
| Pin 50 | I/O — User I/O pin (PF5) |
| Pin 51 | GND — Ground reference |
| Pin 52 | I/O — User I/O pin (PF6) |
| Pin 53 | I/O — User I/O pin (PF7) |
| Pin 54 | I/O — User I/O pin (PG0) |
| Pin 55 | I/O — User I/O pin (PG1) |
| Pin 56 | I/O — User I/O pin (PG2) |
| Pin 57 | I/O — User I/O pin (PG3) |
| Pin 58 | I/O — User I/O pin (PG4) |
| Pin 59 | I/O — User I/O pin (PG5) |
| Pin 60 | I/O — User I/O pin (PG6) |
| Pin 61 | I/O — User I/O pin (PG7) |
| Pin 62 | VCC — 3.3 V core supply |
| Pin 63 | I/O — User I/O pin (PH0) |
| Pin 64 | I/O — User I/O pin (PH1) |
| Pin 65 | I/O — User I/O pin (PH2) |
| Pin 66 | I/O — User I/O pin (PH3) |
| Pin 67 | I/O — User I/O pin (PH4) |
| Pin 68 | I/O — User I/O pin (PH5) |
| Pin 69 | I/O — User I/O pin (PH6) |
| Pin 70 | I/O — User I/O pin (PH7) |
| Pin 71 | DONE — Configuration complete indicator (open-drain) |
| Pin 72 | CCLK — Configuration clock input |
| Pin 73 | DIN — Configuration data serial input |
| Pin 74 | DOUT — Configuration data serial output (daisy-chain) |
| Pin 75 | INIT/RESET — Initialization / configuration reset, active-low open-drain |
| Pin 76 | M0 — Configuration mode select bit 0 |
| Pin 77 | M1 — Configuration mode select bit 1 |
| Pin 78 | M2 — Configuration mode select bit 2 |
| Pin 79 | PWRDWN — Power-down control (used in master mode) |
| Pin 80 | TCLKIN — JTAG / boundary-scan clock input |
| Pin 81 | TDI — JTAG / boundary-scan data input |
| Pin 82 | TDO — JTAG / boundary-scan data output |
| Pin 83 | TMS — JTAG / boundary-scan mode select |
| Pin 84 | VCC — 3.3 V core supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
XC3090L-8PC84I is suitable for 7 applications: Legacy Industrial Glue Logic, Telecommunications Line-Card Interface, Test & Measurement Fixtures, Aerospace & Defense Subsystems, Custom Hardware Bus Interfaces, Digital State-Machine Controllers, Retro-Computing & Emulation Projects.
Legacy Industrial Glue Logic
The XC3090L-8PC84I fits legacy industrial glue-logic boards because its 6,000 gates and 320 CLBs comfortably handle bus-arbitration, address decoding, and custom state machines that would otherwise consume dozens of 74-series TTL packages. The 80 MHz toggle rate is more than sufficient for ISA-style peripheral interfacing, and the 84-pin PLCC footprint allows drop-in replacement of original XC3090A designs. Engineers maintaining long-lifecycle factory-automation lines appreciate the part's mature XACTstep toolchain, which still produces reliable bitstreams from legacy schematics. The 3.3 V core supply reduces power dissipation versus the 5 V XC3090, important in sealed control cabinets with limited airflow. A practical trade-off is that new designs should not start on this part because of obsolete status - it is best reserved for maintenance of installed equipment.
Recommended
Telecommunications Line-Card Interface
The XC3090L-8PC84I is well suited to telecom line-card interface logic because its 70 user I/Os provide sufficient pins for parallel TDM bus interfaces, framing circuits, and per-channel control registers, while its programmable TTL/CMOS input thresholds allow direct connection to mixed-voltage line-driver ICs. The 80 MHz internal toggle frequency easily supports E1/T1 framing rates and HDLC-style protocol engines commonly built in XC3000-series designs. Its SRAM-based configuration allows field reconfiguration through an external PROM, useful for protocol updates. Long-term installed telecom base stations and PBX line cards continue to use this part because re-qualification of modern FPGAs is expensive. Engineers should treat it strictly as a maintenance part; new line-card designs should use current-generation low-power FPGAs with hardware encryption engines.
Recommended
Test & Measurement Fixtures
The XC3090L-8PC84I is a natural fit for custom test-and-measurement fixtures because engineers can program parallel stimulus generation, response capture, and timing-pattern logic in a single device without spinning a new PCB for every protocol. Its 6,000-gate capacity accommodates typical pattern-generator and signature-analyzer functions, while the 70 I/Os are sufficient to drive dozens of test points simultaneously. The 3.3 V core reduces heat in enclosed benchtop instruments, and the 84-pin PLCC allows socketed programming for rapid board bring-up. Because XACTstep supports schematic capture, simulation, and timing analysis, the part is widely used in ATE and lab-instrument designs that have accumulated around it for two decades. The trade-off is that the obsolete lifecycle means fixtures are no longer in active production and must be sourced through secondary channels.
Recommended
Aerospace & Defense Subsystems
The XC3090L-8PC84I is found in aerospace and defense subsystems because its mature bitstream format and known in-service behavior have been validated across decades of deployment, allowing long-term maintenance without re-qualifying new FPGAs under DO-254 or MIL-STD-810 processes. The 3.3 V core and 80 MHz toggle rate are sufficient for avionics-bus bridging, redundant-channel control, and radar-timing subsystems in legacy platforms. The industrial -40 °C to +85 °C temperature grade supports the environmental envelopes typical of military vehicle and rotary-wing applications. Critical pitfall: because the part is obsolete, designers must qualify multiple date codes and ensure configuration-PROM obsolescence is also managed. New defense programs should not start on this FPGA.
Recommended
Custom Hardware Bus Interfaces
The XC3090L-8PC84I is widely deployed in custom-hardware bus-interface adapters because it can implement arbitrary bus protocols (VME, Multibus, custom parallel buses) in a single device with deterministic timing. The 70 I/Os handle address, data, and control signals of legacy 16- and 32-bit bus standards, while the 6,000-gate capacity is sufficient for protocol state machines and DMA engines. The 3.3 V core reduces supply current in densely populated backplane cards. Engineers maintaining legacy VMEbus SBCs and industrial PCs continue to use this part because the alternative is redesigning a board whose entire ecosystem is qualified. Like other XC3000 applications, this is a maintenance-only use case; new bus-interface designs should use modern FPGAs with built-in transceivers and IP cores.
Recommended
Digital State-Machine Controllers
The XC3090L-8PC84I suits digital state-machine controllers such as sequencing ASICs, motor-control pre-processors, and discrete-event simulators because each Configurable Logic Block can implement a small FSM, and the 320 CLBs allow up to dozens of cooperating state machines in one device. The 80 MHz toggle rate easily handles microsecond-resolution sequencing common in stepper-motor and process-control applications. The 84-pin PLCC package is socketable, which simplifies prototype bring-up and in-field firmware updates. The 3.3 V core and industrial temperature grade support a wide range of cabinet and machine-mount environments. Maintenance is the primary use case; new state-machine designs should consider CPLDs or low-end FPGAs with modern toolchains and indefinite supply commitments.
Recommended
Retro-Computing & Emulation Projects
The XC3090L-8PC84I is popular among retro-computing hobbyists and hardware emulators who use the device to re-implement classic 8-bit and 16-bit computer architectures (Apple II expansion cards, IBM PC bus peripherals, arcade boards) where the original bipolar logic is no longer available. Its 6,000 gates can host a small 6502 or Z80 bus interface plus ROM/RAM glue, and the 70 I/Os provide enough pins for address/data busses and peripheral control. The 84-pin PLCC through-hole package is breadboard-friendly, unlike modern BGA FPGAs, which is a key reason hobbyists prefer the XC3000 family over newer parts. Engineers should note that the obsolete XACTstep toolchain can still be found in legacy archives, but the bitstream format is well documented in academic literature.
Recommended
Recommended Products Summary
Engineering reference data for XC3090L-8PC84I — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | XC3090L-8PC84C | XC3090L-7TQG176I | XC3090L-100PC84C | XC3090L-125PC84C | XC3090L-8PC84BKJ |
|---|---|---|---|---|---|---|
| Brand | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx |
| Package | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) - same | 176-pin TQFP - same die, different footprint | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same | 84-pin PLCC (J-Lead) - same |
| Gates | 6,000 | 6,000 | 6,000 | 6,000 | 6,000 | 6,000 |
| Configurable Logic Blocks | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/O | 70 | 70 | up to 138 | 70 | 70 | 70 |
| Maximum Toggle Frequency | 80 MHz | 80 MHz | 70-80 MHz (speed grade 7) | ~70 MHz (speed grade 100) | ~60 MHz (speed grade 125) | 80 MHz |
| Core Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Temperature Grade | Industrial (-40 °C to +85 °C) | Commercial (0 °C to +70 °C) | Industrial (-40 °C to +85 °C) | Commercial (0 °C to +70 °C) | Commercial (0 °C to +70 °C) | Industrial (per BKJ variant) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade in the canonical 84-pin PLCC package (vs XC3090L-8PC84C)
- Same-family drop-in compatibility at the bitstream level (vs XC3190A-4PC84I)
- Low-voltage 3.3 V core versus the original 5 V XC3090 (vs XC3090A-7PC84I)
Design Notes
Provide a clean 3.3 V supply with at least one 0.1 µF ceramic decoupling capacitor per VCC pin (pins 12, 38, 62, 84 on the 84-pin PLCC) plus a single 10 µF bulk capacitor near the package. Although the XC3090L is a low-voltage variant of the original 5 V XC3090, inrush current during configuration bitstream loading can exceed steady-state operating current, so the regulator must have adequate headroom. Estimated steady-state current at 80 MHz internal toggle with 50% I/O switching is approximately 50-100 mA; verify against your design's actual switching activity before sizing the regulator.
The XC3090L-8PC84I uses SRAM-based configuration, so the bitstream is volatile and must be reloaded at every power-up from an external configuration PROM (typically an XC1736 or compatible) or via microprocessor slave-mode loading. Failing to provide a valid configuration source renders the device non-functional even though silicon is healthy. Do not assume that any XC3090-series part can self-configure from on-chip memory - this family has no on-chip non-volatile storage. For prototype bring-up, a JTAG download cable (Xilinx HW-130 or compatible) is essential for direct bitstream injection.
The 84-pin PLCC J-lead package has a 1.27 mm pitch and is socketable; lay out the PCB with a PLCC socket footprint rather than direct soldering if the design must support in-field reprogramming or maintenance replacement of obsolete stock. Keep configuration clock (CCLK, pin 72) traces short and isolated from high-speed I/O switching to avoid configuration bit errors during power-up. Route JTAG signals (TDI/TDO/TMS/TCK, pins 80-83) as a single bus with a 10 kΩ pull-up on TDI/TMS per IEEE 1149.1 to ensure stable boundary-scan operation.
At 80 MHz internal toggle with typical 50% I/O switching, the XC3090L-8PC84I dissipates roughly 0.3-0.5 W; this is well within the 84-pin PLCC's thermal capability even in sealed industrial enclosures without forced air. However, in high-ambient (>70 °C) environments with full industrial temperature grading, derate the toggle rate or switching activity to keep junction temperature below 125 °C. The plastic PLCC package does not have an exposed thermal pad, so all heat is removed through the leads and the PCB copper - a copper pour of at least 1 sq inch on the top and bottom layers under the part is recommended.
Compliance Information
RoHS, REACH, lead-free, halogen-free, and conflict-mineral status were not stated in the verified web data for this obsolete part; XAIPART cannot confirm compliance. Engineers should request a Compliance Statement directly from the distributor's quality organization before using this part in any RoHS- or REACH-regulated market.
