2ED2103S06FXUMA1 vs 2ED21064S06JXUMA1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 2ED2103S06FXUMA1 sa pamamagitan ng Infineon at 2ED21064S06JXUMA1 sa pamamagitan ng Infineon. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Infineon
2ED21064S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon
2ED21064S06JXUMA1 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 2ED2103S06FXUMA1 | 2ED21064S06JXUMA1 |
|---|---|---|
| Brand | Infineon | Infineon |
| Kategorya | Power MOSFET Drivers | Power MOSFET Drivers |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Fungsi | Half-Bridge Gate Driver | High-Side and Low-Side Gate Driver |
| Configuration | Non-Inverting | Half-Bridge (2 outputs, non-inverting) |
| Technology | High-Voltage Level Shift (SOI) | — |
| Number of Drivers | 2 (high-side + low-side) | — |
| Driven Device Type | IGBT, N-Channel MOSFET | — |
| High-Side Offset Voltage (Max) | 650 V | — |
| Bootstrap Voltage (Max) | 675 V | — |
| Supply Voltage (VCC) | 10 V to 20 V | 10 V to 20 V |
| Source Current (typ.) | 0.29 A | — |
| Sink Current (typ.) | 0.7 A | — |
| Bootstrap Diode | Integrated | Integrated |
| Logic Input Compatibility | 3.3 V / 5 V | — |
| Under-Voltage Lockout (UVLO) | Yes (VCC and VBS) | — |
| Packhaging | PG-DSO-8-69 (DSO-8 with exposed pad) | PG-DSO-14 (14-pin SOIC) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Hanay ng Temperature na Operasyon | -40C to +125C | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | Compliant | ROHS3 Compliant |
| Topolohiya | — | High-Side, Low-Side with integrated bootstrap diode |
| Maximum Offset / Boot Voltage | — | 650 V |
| Source Current (typical) | — | 0.29 A |
| Sink Current (typical) | — | 0.7 A |
| Rise Time (typical) | — | [DATA_NEEDED: rise time] |
| Fall Time (typical) | — | [DATA_NEEDED: fall time] |
| Propagation Delay (typical) | — | 100 ns |
| Channel-to-Channel Delay Match | — | [DATA_NEEDED: channel-to-channel delay match] |
| Under-Voltage Lockout | — | Yes (both channels) |
| Input Logic Compatibility | — | 3.3 V / 5 V CMOS |
| Temperature na Operasyon | — | -40C to +125C |
| Negative Gate Drive Robustness | — | -0.7 V |