EP3SE260H780C4L vs EP3SE260H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260H780C4L sa pamamagitan ng Intel at EP3SE260H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3SE260H780C4L | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | Stratix III E | — |
| Logic Elements | 255,000 | — |
| LABs/CLBs | 10,200 | — |
| Total RAM Bits | 16,672,768 (16.7 Mbit) | — |
| User I/O Count | 488 | — |
| Packhaging | 780-ball FCBGA (HBGA 33x33 mm) | 780-BBGA, FCBGA (H780) |
| Speed Grade | C4 (middle/slow tier) | — |
| Core Voltage | 0.9 V (nominal) | — |
| Temperature ng Junction na Operasyon | 0C to +85C (commercial) | — |
| Uri ng Pagpapasok | Surface Mount (flip-chip BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant (lead-free per datasheet) | Compliant (lead-free 'N' suffix) |
| Transceivers | Up to 24 multi-gigabit transceivers | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| Memory Interface | DDR3, DDR2, QDRII+, RLDRAM II controllers | — |
| Configuration Mode | PS, FPP, JTAG with EPCS/EPCQ | — |
| Series | — | Stratix® III E |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| User I/Os | — | 488 |
| Number of Pins / Balls | — | 780 |
| Temperature na Operasyon | — | 0 °C to +85 °C (C grade, commercial) |
| Process Technology | — | 40 nm CMOS |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |