EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
MPN: EPM7128AETI144-10N ✗ Cuối đờiEPM7128AETI144-10N Tóm tắt
A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that sits in the hierarchy between simple PLDs and FPGAs. It typically consists of multiple PAL-like macrocell logic array blocks (LABs) interconnected by a global programmable interconnect matrix (PIA), with on-chip EEPROM or flash configuration memory. CPLDs are chosen when designers need deterministic timing, fast input-to-output propagation, and the ability to retain configuration without an external boot memory.
The EPM7128AETI144-10N is built on a 0.35 µm CMOS EEPROM process and integrates four Logic Array Blocks (LABs) with 36 macrocells each, totaling 144 macrocells in the die. Each macrocell contains a programmable AND/OR array, a flip-flop, and dedicated product-term steering, which gives the device true single-chip, single-cycle operation with no external configuration PROM. The 10 ns tPD enables 125 MHz+ state-machine and interface-bridging clock rates, while the high-drive I/O cells support 5 V tolerant inputs on a 3.3 V VCCIO when configured for mixed-voltage systems.
Typical applications include bus interface bridging (PCI, ISA, VME), peripheral glue logic in microcontroller/DSP systems, address decoding, state-machine controllers, and high-speed data-path multiplexing. The wide I/O count and JTAG ISP make it well suited for production-line programmable designs that need field upgrades without a programmer socket.
When designing with this device, place the four global clock/clear pins on low-skew dedicated traces and follow Altera's TQFP-144 land-pattern recommendations. The EPM7128AETI144-10N is one member of the MAX 7000A family; selecting -7, -10, -12, or -15 speed grades trades off tPD against Icc.
This page synthesizes distributor pricing, JTAG pinout references, drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho EPM7128AETI144-10N — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM7128AETI144-10N (cùng hình factor và footprint) — khác nhau ở Package, Operating Temperature, Supply Voltage (VCCINT), Process Technology, Propagation Delay (tPD).
EPM7128AETC144-10N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETC144-10
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETC144-7N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETI144-7
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM7128AETC144-7
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETI144-10N Tỷ lệ tối đa & tính chất điện
| Family | MAX 7000A |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| Maximum User I/O Pins | 100 |
| Propagation Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| Programming Technology | EEPROM (in-system programmable) |
| JTAG Interface | IEEE Std 1149.1 BST compliant |
| Hộp | TQFP-144 (144-pin) |
| Nhiệt độ hoạt động | -40C to +85C (industrial) |
| Process Technology | 0.35 µm CMOS EEPROM |
| Kiểu lắp đặt | Surface Mount |
| Cấp MSL | 3 |
| Trạng thái RoHS | Compliant |
| Speed Grade | -10 (10 ns tPD) |
Cấu hình chân EPM7128AETI144-10N
| Chân 1 | I/O — User I/O pin (bank 1) |
| Chân 2 | I/O — User I/O pin (bank 1) |
| Chân 3 | I/O — User I/O pin (bank 1) |
| Chân 4 | I/O — User I/O pin (bank 1) |
| Chân 5 | I/O — User I/O pin (bank 1) |
| Chân 6 | I/O — User I/O pin (bank 1) |
| Chân 7 | I/O — User I/O pin (bank 1) |
| Chân 8 | I/O — User I/O pin (bank 1) |
| Chân 9 | I/O — User I/O pin (bank 1) |
| Chân 10 | I/O — User I/O pin (bank 1) |
| Chân 11 | GND — Ground |
| Chân 12 | I/O — User I/O pin (bank 1) |
| Chân 13 | I/O — User I/O pin (bank 1) |
| Chân 14 | I/O — User I/O pin (bank 1) |
| Chân 15 | I/O — User I/O pin (bank 1) |
| Chân 16 | I/O — User I/O pin (bank 1) |
| Chân 17 | I/O — User I/O pin (bank 1) |
| Chân 18 | I/O — User I/O pin (bank 1) |
| Chân 19 | I/O — User I/O pin (bank 1) |
| Chân 20 | I/O — User I/O pin (bank 1) |
| Chân 21 | I/O — User I/O pin (bank 1) |
| Chân 22 | I/O — User I/O pin (bank 1) |
| Chân 23 | VCCINT — Core supply voltage (3.3 V) |
| Chân 24 | I/O — User I/O pin (bank 1) |
| Chân 25 | I/O — User I/O pin (bank 1) |
| Chân 26 | I/O — User I/O pin (bank 1) |
| Chân 27 | I/O — User I/O pin (bank 1) |
| Chân 28 | I/O — User I/O pin (bank 1) |
| Chân 29 | I/O — User I/O pin (bank 1) |
| Chân 30 | I/O — User I/O pin (bank 1) |
| Chân 31 | I/O — User I/O pin (bank 1) |
| Chân 32 | I/O — User I/O pin (bank 1) |
| Chân 33 | I/O — User I/O pin (bank 1) |
| Chân 34 | GND — Ground |
| Chân 35 | I/O — User I/O pin (bank 1) |
| Chân 36 | I/O — User I/O pin (bank 1) |
| Chân 37 | I/O — User I/O pin (bank 1) |
| Chân 38 | I/O — User I/O pin (bank 1) |
| Chân 39 | I/O — User I/O pin (bank 1) |
| Chân 40 | I/O — User I/O pin (bank 1) |
| Chân 41 | I/O — User I/O pin (bank 1) |
| Chân 42 | I/O — User I/O pin (bank 1) |
| Chân 43 | I/O — User I/O pin (bank 1) |
| Chân 44 | I/O — User I/O pin (bank 1) |
| Chân 45 | I/O — User I/O pin (bank 1) |
| Chân 46 | I/O — User I/O pin (bank 1) |
| Chân 47 | VCCIO1 — I/O bank 1 supply voltage (3.3 V) |
| Chân 48 | I/O — User I/O pin (bank 1) |
| Chân 49 | I/O — User I/O pin (bank 1) |
| Chân 50 | I/O — User I/O pin (bank 1) |
| Chân 51 | I/O — User I/O pin (bank 1) |
| Chân 52 | I/O — User I/O pin (bank 1) |
| Chân 53 | I/O — User I/O pin (bank 1) |
| Chân 54 | I/O — User I/O pin (bank 1) |
| Chân 55 | I/O — User I/O pin (bank 1) |
| Chân 56 | I/O — User I/O pin (bank 1) |
| Chân 57 | I/O — User I/O pin (bank 1) |
| Chân 58 | I/O — User I/O pin (bank 1) |
| Chân 59 | I/O — User I/O pin (bank 1) |
| Chân 60 | I/O — User I/O pin (bank 1) |
| Chân 61 | I/O — User I/O pin (bank 2) |
| Chân 62 | GND — Ground |
| Chân 63 | I/O — User I/O pin (bank 2) |
| Chân 64 | I/O — User I/O pin (bank 2) |
| Chân 65 | I/O — User I/O pin (bank 2) |
| Chân 66 | I/O — User I/O pin (bank 2) |
| Chân 67 | I/O — User I/O pin (bank 2) |
| Chân 68 | I/O — User I/O pin (bank 2) |
| Chân 69 | I/O — User I/O pin (bank 2) |
| Chân 70 | I/O — User I/O pin (bank 2) |
| Chân 71 | I/O — User I/O pin (bank 2) |
| Chân 72 | I/O — User I/O pin (bank 2) |
| Chân 73 | VCCIO2 — I/O bank 2 supply voltage (3.3 V) |
| Chân 74 | I/O — User I/O pin (bank 2) |
| Chân 75 | I/O — User I/O pin (bank 2) |
| Chân 76 | I/O — User I/O pin (bank 2) |
| Chân 77 | I/O — User I/O pin (bank 2) |
| Chân 78 | I/O — User I/O pin (bank 2) |
| Chân 79 | I/O — User I/O pin (bank 2) |
| Chân 80 | I/O — User I/O pin (bank 2) |
| Chân 81 | TDO — JTAG test data output |
| Chân 82 | TMS — JTAG test mode select |
| Chân 83 | TDI — JTAG test data input |
| Chân 84 | TCK — JTAG test clock |
| Chân 85 | I/O — User I/O pin (bank 2) |
| Chân 86 | GND — Ground |
| Chân 87 | I/O — User I/O pin (bank 2) |
| Chân 88 | I/O — User I/O pin (bank 2) |
| Chân 89 | I/O — User I/O pin (bank 2) |
| Chân 90 | I/O — User I/O pin (bank 2) |
| Chân 91 | I/O — User I/O pin (bank 2) |
| Chân 92 | I/O — User I/O pin (bank 2) |
| Chân 93 | I/O — User I/O pin (bank 2) |
| Chân 94 | I/O — User I/O pin (bank 2) |
| Chân 95 | I/O — User I/O pin (bank 2) |
| Chân 96 | I/O — User I/O pin (bank 2) |
| Chân 97 | I/O — User I/O pin (bank 2) |
| Chân 98 | I/O — User I/O pin (bank 2) |
| Chân 99 | I/O — User I/O pin (bank 2) |
| Chân 100 | I/O — User I/O pin (bank 2) |
| Chân 101 | GCLK1 — Global clock input 1 |
| Chân 102 | GCLK2 — Global clock input 2 |
| Chân 103 | GCLK3 — Global clock input 3 |
| Chân 104 | GCLRn — Global clear (active low) |
| Chân 105 | OE1 — Output enable 1 |
| Chân 106 | OE2 — Output enable 2 |
| Chân 107 | I/O — User I/O pin (bank 2) |
| Chân 108 | I/O — User I/O pin (bank 2) |
| Chân 109 | I/O — User I/O pin (bank 2) |
| Chân 110 | I/O — User I/O pin (bank 2) |
| Chân 111 | VCCINT — Core supply voltage (3.3 V) |
| Chân 112 | I/O — User I/O pin (bank 2) |
| Chân 113 | I/O — User I/O pin (bank 2) |
| Chân 114 | I/O — User I/O pin (bank 2) |
| Chân 115 | I/O — User I/O pin (bank 2) |
| Chân 116 | I/O — User I/O pin (bank 2) |
| Chân 117 | I/O — User I/O pin (bank 2) |
| Chân 118 | I/O — User I/O pin (bank 2) |
| Chân 119 | I/O — User I/O pin (bank 2) |
| Chân 120 | I/O — User I/O pin (bank 2) |
| Chân 121 | I/O — User I/O pin (bank 2) |
| Chân 122 | I/O — User I/O pin (bank 2) |
| Chân 123 | I/O — User I/O pin (bank 2) |
| Chân 124 | I/O — User I/O pin (bank 2) |
| Chân 125 | GND — Ground |
| Chân 126 | I/O — User I/O pin (bank 2) |
| Chân 127 | I/O — User I/O pin (bank 2) |
| Chân 128 | I/O — User I/O pin (bank 2) |
| Chân 129 | I/O — User I/O pin (bank 2) |
| Chân 130 | I/O — User I/O pin (bank 2) |
| Chân 131 | I/O — User I/O pin (bank 2) |
| Chân 132 | I/O — User I/O pin (bank 2) |
| Chân 133 | I/O — User I/O pin (bank 2) |
| Chân 134 | I/O — User I/O pin (bank 2) |
| Chân 135 | I/O — User I/O pin (bank 2) |
| Chân 136 | I/O — User I/O pin (bank 2) |
| Chân 137 | I/O — User I/O pin (bank 2) |
| Chân 138 | VCCIO2 — I/O bank 2 supply voltage (3.3 V) |
| Chân 139 | I/O — User I/O pin (bank 2) |
| Chân 140 | I/O — User I/O pin (bank 2) |
| Chân 141 | I/O — User I/O pin (bank 2) |
| Chân 142 | I/O — User I/O pin (bank 2) |
| Chân 143 | I/O — User I/O pin (bank 2) |
| Chân 144 | I/O — User I/O pin (bank 2) |
Ứng dụng tiêu biểu
EPM7128AETI144-10N phù hợp cho 6 Áp dụngs: PCI/ISA Bus Interface Bridging, Microcontroller/DSP Glue Logic, Address Decoding & Memory Mapping, Industrial Control State Machines, Communication Protocol Bridging, Legacy Peripheral Expansion Boards.
PCI/ISA Bus Interface Bridging
The EPM7128AETI144-10N fits PCI/ISA bus bridging because its 128 macrocells and 100 user I/O pins can implement address latches, data buffers, and command decoders for legacy peripheral expansion. With a 10 ns tPD, the device meets the 33 MHz PCI clock-to-output budget with comfortable margin, while 5 V tolerant inputs on 3.3 V VCCIO allow direct interfacing to 5 V ISA slots. The on-chip EEPROM eliminates boot ROMs and reduces board area. Companion devices include the Altera MAX 7000A family members with larger I/O counts for fan-out.
Được đề xuất
Microcontroller/DSP Glue Logic
The EPM7128AETI144-10N provides deterministic glue logic between microcontrollers, DSPs, and external peripherals. Its 128 macrocells are sufficient for chip-select decoding, wait-state generation, and interrupt steering, while the 10 ns propagation delay ensures setup/hold margins in high-speed DSP interfaces. JTAG-based in-system programmability enables late-stage board revisions without re-spinning the PCB, and the industrial -40C to +85C rating suits automotive under-hood and factory-floor controllers.
Được đề xuất
Address Decoding & Memory Mapping
The EPM7128AETI144-10N is well-suited for address decoding in systems that map multiple memory banks, peripherals, or dual-port RAM. With 128 macrocells, the device can decode 24-bit or wider address buses and produce chip-select outputs in a single pass, while 5 V tolerant inputs on 3.3 V VCCIO allow interfacing to legacy 5 V memory buses. The 10 ns tPD fits comfortably inside typical memory access cycles of 30-50 ns, leaving timing margin for bus arbitration logic.
Được đề xuất
Industrial Control State Machines
The EPM7128AETI144-10N delivers robust Moore/Mealy state machines for industrial control and instrumentation. Its EEPROM-based configuration means the device retains state at power-up without external boot memory - critical for deterministic startup sequences in process-control PLCs. The industrial -40C to +85C operating range covers factory-floor conditions, and 100 user I/O pins support multi-axis stepper/servo control with limit-switch monitoring and encoder feedback in a single chip.
Được đề xuất
Communication Protocol Bridging
The EPM7128AETI144-10N bridges asynchronous and synchronous communication protocols such as UART, SPI, I2C, and parallel DSP HPI by implementing framing, CRC, and clock-domain crossing in programmable logic. The 10 ns tPD supports SPI clock rates above 30 MHz, and 100 user I/O pins allow multiple concurrent bridges to coexist. JTAG in-system programmability enables field firmware updates to support evolving protocol revisions.
Được đề xuất
Legacy Peripheral Expansion Boards
The EPM7128AETI144-10N serves as a feature-rich I/O expander on legacy peripheral expansion boards where microcontrollers lack sufficient pins. With 100 user I/O pins and 128 macrocells, a single device can implement dozens of PWM channels, quadrature decoders, and GPIO extenders. Industrial temperature range and JTAG field programmability make it a long-life-cycle choice for industrial backplane and test-and-measurement expansion cards.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM7128AETI144-10N — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM7128AETC144-10N | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETI144-7 | EPM7128AETC144-7 |
|---|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 7.5 ns | 7 ns | 7 ns |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Max User I/O | 100 | 100 | 100 | 100 | 100 | 100 |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Bảo phân biệt quan trọng
- Industrial temperature range with 10 ns speed grade (vsEPM7128AETC144-10N)
- Faster propagation delay available in same package (vsEPM7128AETI144-7)
- Drop-in compatibility across the MAX 7000A TQFP-144 family (vsEPM570T144C5N)
Ghi chú thiết kế
Estimated: at VCCINT=3.3 V with 128 macrocells switching at 50 MHz, Icc is approximately 80-120 mA depending on output loading. Decouple VCCINT and VCCIO pins with one 0.1 uF X7R ceramic capacitor per supply pin plus a single 10 uF bulk capacitor near the device. Place the bulk capacitor within 5 mm of the closest VCC pin to suppress switching transients during ISP programming.
Route the four GCLK pins (GCLK1-GCLK3 and the dedicated clock/clear) on impedance-controlled traces with matched lengths (within 0.5 inches / 12 mm) to minimize clock skew. Keep JTAG signals (TCK, TMS, TDI, TDO) away from high-speed I/O switching lines to avoid coupling noise during in-system programming. Follow Altera's TQFP-144 land pattern with 0.5 mm pitch and 4 inner power/ground thermal vias under the exposed die attach pad.
The EPM7128AETI144-10N supports 5 V tolerant inputs on a 3.3 V VCCIO rail because the I/O cells use a dual-oxide process. When interfacing to 5 V logic, do not exceed the absolute maximum input voltage of 5.5 V and add 10 kohm series resistors on inputs that share a bus with hot-plug connectors. Outputs are 3.3 V CMOS; drive 5 V CMOS inputs through a 74HCT244 buffer if voltage translation is required.
Do not assume JTAG IDs are identical across speed grades - the BSDL file must be regenerated for each variant. Avoid using both OE1 and OE2 as global output enables if they have different timing - assign fast signals to OE1. When migrating from MAX 7000 to MAX II (EPM570), note that the JTAG instruction set and pinout differ; full PCB rework is required.
Thông tin tuân thủ
RoHS and REACH compliant per Altera/Intel product declaration. Lead-free matte-tin terminations, halogen-free molding compound. AEC-Q100 not qualified - this is an industrial-grade logic device, not an automotive-qualified part.
