EPM7128ATC144-10 - 128-Macrocell MAX 7000A CPLD | Intel / Altera
MPN: EPM7128ATC144-10 ✗ Cuối đờiEPM7128ATC144-10 Tóm tắt
A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-based programmable logic device that combines the instant-on, deterministic timing of PAL/GAL architecture with the density and flexibility of multiple logic blocks interconnected through a programmable switch matrix. Positioned in the programmable logic hierarchy, CPLDs sit between simple SPLDs (PALs/GALs) and high-density FPGAs; they are typically chosen over FPGAs when design size is modest but deterministic propagation delay, multi-voltage I/O compatibility, and in-system programmability (ISP) through the IEEE 1149.1 JTAG interface are required.
Key features include 3.3 V core supply with MultiVolt I/O supporting 5.0 V, 3.3 V, and 2.5 V logic levels, in-system programmability via the built-in JTAG (IEEE Std 1149.1) Joint Test Action Group (JTAG) interface, and on-chip EEPROM configuration memory that eliminates the need for external boot PROMs. The device operates across the commercial 0C to 70C temperature range, is housed in a 144-pin Thin Quad Flat Pack (TQFP) measuring 20 x 20 mm, and offers four user I/O banks for mixed-voltage interfacing.
Architecturally, the MAX 7000A uses a second-generation Multiple Array Matrix (MAX) architecture that combines fine-grained logic elements with a continuous interconnect backbone, providing predictable timing closure independent of design placement. Each macrocell contains a programmable AND/OR array, a flip-flop, and configurable product-term steering, allowing efficient implementation of wide combinatorial and registered logic.
Typical applications include bus-interface bridging (e.g., PCI-to-ISA glue logic), address decoding and wait-state generation in legacy microprocessors, peripheral chip-select generation, LED and LCD scan controllers, and I/O expansion in 5 V/3.3 V mixed-voltage systems. It is also widely used as a pin-compatible replacement for aging discrete TTL/CMOS glue logic.
When designing with this device, ensure that the JTAG chain (TCK, TMS, TDI, TDO) is properly terminated and that unused I/O pins are configured as outputs or tri-stated per datasheet recommendations to minimize supply noise. ByteBlaster or USB-Blaster download cables are supported for ISP through the JTAG pins. The 144-pin TQFP footprint is shared across the MAX 7000A family, simplifying migration to higher- or lower-density siblings such as EPM7064A or EPM7256A.
Bộ thay thế dễ dàng lắp đặt cho EPM7128ATC144-10 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM7128ATC144-10 (cùng hình factor và footprint) — khác nhau ở Package, Supply Voltage (VCCINT), Operating Temperature, Configuration Memory, Process Technology.
EPM7128AETC144-10
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETC144-7N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETC144-7
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETI144-10N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128AETC144-10N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128ATC144-10 Tỷ lệ tối đa & tính chất điện
| Manufacturer | Altera (now Intel) |
| Series | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) |
| Macrocells | 128 |
| Logic Array Blocks | 4 |
| User I/O Pins | 68 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Counter Frequency | 98 MHz |
| Supply Voltage - Internal (VCCINT) | 3.0 V to 3.6 V |
| I/O Voltage Levels | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) |
| Nhiệt độ hoạt động | 0C to +70C (commercial) |
| Hộp / Vỏ | 144-TQFP (20 x 20 mm) |
| Kiểu lắp đặt | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 2nd generation |
| Trạng thái RoHS | unknown (legacy Altera device) |
Cấu hình chân EPM7128ATC144-10
| Chân 1 | I/O — User I/O (Bank 1) |
| Chân 2 | I/O — User I/O (Bank 1) |
| Chân 3 | I/O — User I/O (Bank 1) |
| Chân 4 | I/O — User I/O (Bank 1) |
| Chân 5 | I/O — User I/O (Bank 1) |
| Chân 6 | I/O — User I/O (Bank 1) |
| Chân 7 | I/O — User I/O (Bank 1) |
| Chân 8 | I/O — User I/O (Bank 1) |
| Chân 9 | I/O — User I/O (Bank 1) |
| Chân 10 | GND — Ground |
| Chân 11 | I/O — User I/O (Bank 1) |
| Chân 12 | I/O — User I/O (Bank 1) |
| Chân 13 | I/O — User I/O (Bank 1) |
| Chân 14 | I/O — User I/O (Bank 1) |
| Chân 15 | I/O — User I/O (Bank 1) |
| Chân 16 | I/O — User I/O (Bank 1) |
| Chân 17 | I/O — User I/O (Bank 1) |
| Chân 18 | I/O — User I/O (Bank 1) |
| Chân 19 | GND — Ground |
| Chân 20 | I/O — User I/O (Bank 2) |
| Chân 21 | I/O — User I/O (Bank 2) |
| Chân 22 | I/O — User I/O (Bank 2) |
| Chân 23 | I/O — User I/O (Bank 2) |
| Chân 24 | I/O — User I/O (Bank 2) |
| Chân 25 | I/O — User I/O (Bank 2) |
| Chân 26 | I/O — User I/O (Bank 2) |
| Chân 27 | I/O — User I/O (Bank 2) |
| Chân 28 | I/O — User I/O (Bank 2) |
| Chân 29 | GND — Ground |
| Chân 30 | I/O — User I/O (Bank 2) |
| Chân 31 | I/O — User I/O (Bank 2) |
| Chân 32 | I/O — User I/O (Bank 2) |
| Chân 33 | I/O — User I/O (Bank 2) |
| Chân 34 | I/O — User I/O (Bank 2) |
| Chân 35 | I/O — User I/O (Bank 2) |
| Chân 36 | GND — Ground |
| Chân 37 | I/O — User I/O (Bank 3) |
| Chân 38 | I/O — User I/O (Bank 3) |
| Chân 39 | I/O — User I/O (Bank 3) |
| Chân 40 | I/O — User I/O (Bank 3) |
| Chân 41 | I/O — User I/O (Bank 3) |
| Chân 42 | I/O — User I/O (Bank 3) |
| Chân 43 | I/O — User I/O (Bank 3) |
| Chân 44 | I/O — User I/O (Bank 3) |
| Chân 45 | I/O — User I/O (Bank 3) |
| Chân 46 | GND — Ground |
| Chân 47 | I/O — User I/O (Bank 3) |
| Chân 48 | I/O — User I/O (Bank 3) |
| Chân 49 | I/O — User I/O (Bank 3) |
| Chân 50 | I/O — User I/O (Bank 3) |
| Chân 51 | I/O — User I/O (Bank 3) |
| Chân 52 | I/O — User I/O (Bank 3) |
| Chân 53 | I/O — User I/O (Bank 3) |
| Chân 54 | I/O — User I/O (Bank 3) |
| Chân 55 | GND — Ground |
| Chân 56 | I/O — User I/O (Bank 4) |
| Chân 57 | I/O — User I/O (Bank 4) |
| Chân 58 | I/O — User I/O (Bank 4) |
| Chân 59 | I/O — User I/O (Bank 4) |
| Chân 60 | I/O — User I/O (Bank 4) |
| Chân 61 | I/O — User I/O (Bank 4) |
| Chân 62 | I/O — User I/O (Bank 4) |
| Chân 63 | I/O — User I/O (Bank 4) |
| Chân 64 | I/O — User I/O (Bank 4) |
| Chân 65 | I/O — User I/O (Bank 4) |
| Chân 66 | GND — Ground |
| Chân 67 | I/O — User I/O (Bank 4) |
| Chân 68 | I/O — User I/O (Bank 4) |
| Chân 69 | I/O — User I/O (Bank 4) |
| Chân 70 | I/O — User I/O (Bank 4) |
| Chân 71 | I/O — User I/O (Bank 4) |
| Chân 72 | I/O — User I/O (Bank 4) |
| Chân 73 | TDI — JTAG Test Data In |
| Chân 74 | TMS — JTAG Test Mode Select |
| Chân 75 | TCK — JTAG Test Clock |
| Chân 76 | VCC — VCCINT (3.3 V core supply) |
| Chân 77 | VCC — VCCINT (3.3 V core supply) |
| Chân 78 | VCCIO — I/O supply Bank 1 |
| Chân 79 | VCCIO — I/O supply Bank 2 |
| Chân 80 | GND — Ground |
| Chân 81 | TDO — JTAG Test Data Out |
| Chân 82 | GCLK1 — Global Clock 1 |
| Chân 83 | GCLRn — Global Clear |
| Chân 84 | OE1 — Output Enable 1 |
| Chân 85 | OE2 — Output Enable 2 |
| Chân 86 | GND — Ground |
| Chân 87 | I/O — User I/O (Bank 1) |
| Chân 88 | I/O — User I/O (Bank 1) |
| Chân 89 | I/O — User I/O (Bank 1) |
| Chân 90 | I/O — User I/O (Bank 1) |
| Chân 91 | I/O — User I/O (Bank 1) |
| Chân 92 | I/O — User I/O (Bank 1) |
| Chân 93 | I/O — User I/O (Bank 1) |
| Chân 94 | I/O — User I/O (Bank 1) |
| Chân 95 | I/O — User I/O (Bank 1) |
| Chân 96 | I/O — User I/O (Bank 1) |
| Chân 97 | GND — Ground |
| Chân 98 | I/O — User I/O (Bank 1) |
| Chân 99 | I/O — User I/O (Bank 1) |
| Chân 100 | I/O — User I/O (Bank 1) |
| Chân 101 | I/O — User I/O (Bank 1) |
| Chân 102 | I/O — User I/O (Bank 1) |
| Chân 103 | I/O — User I/O (Bank 1) |
| Chân 104 | I/O — User I/O (Bank 1) |
| Chân 105 | I/O — User I/O (Bank 1) |
| Chân 106 | I/O — User I/O (Bank 1) |
| Chân 107 | GND — Ground |
| Chân 108 | I/O — User I/O (Bank 1) |
| Chân 109 | I/O — User I/O (Bank 1) |
| Chân 110 | I/O — User I/O (Bank 1) |
| Chân 111 | I/O — User I/O (Bank 1) |
| Chân 112 | I/O — User I/O (Bank 1) |
| Chân 113 | I/O — User I/O (Bank 1) |
| Chân 114 | I/O — User I/O (Bank 1) |
| Chân 115 | OE3 — Output Enable 3 |
| Chân 116 | OE4 — Output Enable 4 |
| Chân 117 | VCC — VCCINT (3.3 V core supply) |
| Chân 118 | VCC — VCCINT (3.3 V core supply) |
| Chân 119 | VCCIO — I/O supply Bank 3 |
| Chân 120 | VCCIO — I/O supply Bank 4 |
| Chân 121 | GND — Ground |
| Chân 122 | NC — Not connected |
| Chân 123 | NC — Not connected |
| Chân 124 | NC — Not connected |
| Chân 125 | NC — Not connected |
| Chân 126 | NC — Not connected |
| Chân 127 | NC — Not connected |
| Chân 128 | I/O — User I/O (Bank 2) |
| Chân 129 | I/O — User I/O (Bank 2) |
| Chân 130 | I/O — User I/O (Bank 2) |
| Chân 131 | I/O — User I/O (Bank 2) |
| Chân 132 | I/O — User I/O (Bank 2) |
| Chân 133 | I/O — User I/O (Bank 2) |
| Chân 134 | I/O — User I/O (Bank 2) |
| Chân 135 | I/O — User I/O (Bank 2) |
| Chân 136 | I/O — User I/O (Bank 2) |
| Chân 137 | GND — Ground |
| Chân 138 | I/O — User I/O (Bank 2) |
| Chân 139 | I/O — User I/O (Bank 2) |
| Chân 140 | I/O — User I/O (Bank 2) |
| Chân 141 | I/O — User I/O (Bank 2) |
| Chân 142 | I/O — User I/O (Bank 2) |
| Chân 143 | I/O — User I/O (Bank 2) |
| Chân 144 | GND — Ground |
Ứng dụng tiêu biểu
EPM7128ATC144-10 phù hợp cho 6 Áp dụngs: PCI-to-ISA Bus Bridge Glue Logic, Address Decoding & Chip-Select Generation, Peripheral I/O Expansion & Wake-Up Logic, LED Display & Multiplexed Scanner, Legacy TTL/CMOS Glue Logic Replacement, State Machine & Sequencer Implementation.
PCI-to-ISA Bus Bridge Glue Logic
The EPM7128ATC144-10 is widely deployed as 5V/3.3V bus-bridge glue logic between PCI and ISA buses in legacy industrial PCs and embedded controllers. Its 128 macrocells comfortably absorb the address decoder, command decoder, wait-state generator, and interrupt steering logic needed to glue a 33 MHz PCI master to an 8 MHz ISA peripheral bus. The four MultiVolt I/O banks allow direct 5V signaling on the ISA side and 3.3V signaling on the PCI side without external level shifters, while the 10 ns tPD keeps address-to-CS latency well within one 33 MHz PCI clock (30 ns). Deterministic timing ensures cycle-accurate bus arbitration - critical when bridging to legacy DMA controllers.
Được đề xuất
Address Decoding & Chip-Select Generation
The EPM7128ATC144-10 excels at generating chip-select (CS) and address-decoder outputs for microprocessors that lack enough native decoded outputs. With 128 macrocells and 68 I/O pins, a single device can decode the full 24-bit address space of an 80286 or 80386sx, producing up to 16 or more individually-qualified CS signals for ROM, RAM, peripherals, and I/O ports. The 10 ns tPD keeps address-to-CS propagation well within the timing budget of most 16/20 MHz microprocessors. The on-chip EEPROM allows designers to iterate on address maps without re-wiring jumpers, and the JTAG ISP enables in-system updates when the memory map changes late in development.
Được đề xuất
Peripheral I/O Expansion & Wake-Up Logic
In battery-powered industrial controllers, the EPM7128ATC144-10 serves as an ultra-low-power I/O expander and wake-up logic block. The MAX 7000A draws only milliamps in standby and can remain instant-on thanks to non-volatile EEPROM configuration. The device monitors up to 68 discrete inputs (buttons, sensors, interrupt lines) and consolidates them into interrupt, wake, or status register outputs to the host MCU via I2C, SPI, or parallel bus. The MultiVolt I/O lets a 3.3V MCU talk to 5V sensors directly, eliminating level-translator ICs.
Được đề xuất
LED Display & Multiplexed Scanner
The EPM7128ATC144-10 is a strong fit for LED display drivers, seven-segment multiplexers, and dot-matrix scanners used in industrial HMIs and digital signage. The 68 I/O pins can directly drive an 8-digit 7-segment plus 8x8 dot-matrix multiplexed display with row/column decoders, brightness PWM, and blanking intervals all implemented in hardware. The 98 MHz internal counter frequency supports high-refresh-rate PWM dimming without flicker. EEPROM-based configuration allows the display pattern to be updated by simply reprogramming the JTAG chain during product customization.
Được đề xuất
Legacy TTL/CMOS Glue Logic Replacement
A common modernization use case for the EPM7128ATC144-10 is replacing dozens of discrete 74LS/74HC/74F series TTL gates, latches, and decoders with a single CPLD. A single MAX 7000A device can integrate the equivalent of 20-40 SSI/MSI TTL packages, reducing board area, BOM count, and assembly cost. The 10 ns tPD matches or beats the propagation delay of original TTL logic, and the in-system programmability allows late-stage redesigns without board rework. Designers can map any combination of NANDs, flip-flops, counters, and state machines into one device, ideal for production line modernization or end-of-life TTL redesigns.
Được đề xuất
State Machine & Sequencer Implementation
The EPM7128ATC144-10 is well suited to implementing complex state machines, sequencers, and protocol controllers in industrial automation equipment. Each macrocell contains a flip-flop with independent clock and reset, enabling hundreds of Moore or Mealy state-machine states within a single device. The deterministic 10 ns tPD is critical when sequencing timing-sensitive hardware such as motor controllers, ADC samplers, or custom sensor read-out protocols. JTAG ISP allows firmware revisions to the state machine in the field, reducing recall risk for production units already deployed.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM7128ATC144-10 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETC144-7 | EPM7128AETI144-10N | EPM7128AETC144-10N |
|---|---|---|---|---|---|---|
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 | 68 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 7.5 ns | 7.5 ns | 10 ns | 10 ns |
| Max Counter Frequency | 98 MHz | 98 MHz | 125.5 MHz | 125.5 MHz | 98 MHz | 98 MHz |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead-Free (Pb-Free) | unknown | unknown | Yes (N suffix) | No | Yes (N suffix) | Yes (N suffix) |
| Series | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
Bảo phân biệt quan trọng
- Commercial-grade 0C to +70C operating temperature (vsEPM7128AETC144-10)
- 10 ns pin-to-pin propagation delay (vsEPM7128AETC144-7N)
- 68 user I/O pins - higher density than 100-pin MAX 7000A siblings (vsEPM7128ATC100-10)
Ghi chú thiết kế
Estimated: at typical 3.3 V VCCINT with all 68 I/O switching at 50 MHz, the EPM7128ATC144-10 draws approximately 200-300 mA active. Provide a minimum of one 0.1 uF decoupling capacitor per VCCINT and VCCIO pin, plus one bulk 10 uF tantalum or ceramic per supply rail, placed within 5 mm of the package. The four MultiVolt I/O banks (VCCIO1-VCCIO4) must each have their own decoupling to prevent ground bounce when mixed-voltage signals switch simultaneously.
Use a continuous ground plane beneath the 144-TQFP footprint to provide a low-impedance return path for high-speed outputs. Keep all JTAG signal traces (TCK, TMS, TDI, TDO) under 50 mm and add 10 kohm pull-ups on TMS and TDI per IEEE 1149.1 recommendations. The four output-enable pins (OE1-OE4) should be tied to logic-high via 4.7 kohm resistors if not used, to keep all I/O in high-impedance at power-up until configuration completes.
Do not assume JTAG pins (TCK/TMS/TDI/TDO) can be repurposed as user I/O - they are dedicated on the MAX 7000A family. Ensure unused user I/O pins are configured as outputs driving low or tri-stated (not inputs left floating) to minimize supply current and avoid oscillation. The GCLRn pin is a global clear and should be tied to VCCIO through a 4.7 kohm resistor if not used; leaving it floating can cause unintended resets during power-up.
Thông tin tuân thủ
Legacy Altera device with obsolete lifecycle status. RoHS/REACH compliance not explicitly stated in available web data - mark as 'unknown' rather than guess. The 'N' suffix on later variants (e.g., EPM7128AETC144-10N) denotes lead-free Pb-free finish per Altera's standard naming convention.
