IQE020N04LM6CGATMA1 - 40V 2.0mΩ OptiMOS 6 MOSFET | Infineon
MPN: IQE020N04LM6CGATMA1 ✓ Hoạt độngIQE020N04LM6CGATMA1 Tóm tắt
A power MOSFET is a voltage-controlled semiconductor switch used to efficiently route or modulate current in power-conversion and motor-drive circuits. As a member of the OptiMOS 6 family, the IQE020N04LM6CG belongs to a hierarchy of N-channel enhancement-mode MOSFETs that sit within Infineon's broader low-voltage power MOSFET portfolio, optimized for 25–40 V synchronous rectification, hot-swap, and battery-protection applications. Compared with older OptiMOS 5 generations, OptiMOS 6 reduces figure-of-merit (FOM = RDS(on) × Qg) and improves switching performance at high di/dt.
The package is the key differentiating feature. The source-down, center-gate PQFN 3.3 × 3.3 layout places the thermal pad and source connection on the bottom of the package - the same side that mounts to the PCB. This construction provides a direct thermal path from the die to the board, lowering RthJA substantially versus conventional drain-down QFN packages. It also enables top-side cooling, dual-side cooling, and a simplified PCB layout where the source is the natural ground-return.
Typical applications include 24 V brushless DC (BLDC) motor drives, e-fuse and hot-swap controllers, battery-management systems (BMS) for 1S–10S lithium packs, point-of-load (POL) synchronous buck converters, USB-PD power paths, and 48 V mild-hybrid DC-DC converters. With RDS(on) of ~2.0 mΩ at 10 V VGS, conduction loss at 20 A is roughly 0.8 W, making it suitable for high-current density designs.
Design considerations include VGS(th) gate-drive requirements (10 V drive recommended for full RDS(on) rating), PCB layout to minimize source-inductance in the gate loop, and thermal management via copper area and via arrays. The exposed source-down pad should be soldered to a flooded copper pour for optimum heat spreading.
This page consolidates distributor pricing, drop-in alternative listings, and practical layout guidance that goes beyond the manufacturer's datasheet to accelerate your design and sourcing decisions.
Bộ thay thế dễ dàng lắp đặt cho IQE020N04LM6CGATMA1 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với IQE020N04LM6CGATMA1 (cùng hình factor và footprint) — khác nhau ở Technology, Operating Temperature Range, Package, Drain-Source Voltage (VDS), MSL Level.
IQE036N08NM6CGSCATMA1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →IQE004NE1LM7CGATMA1
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →ISC016N08NM8ATMA1
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →IPT067N20NM6ATMA1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →IQE020N04LM6CGATMA1 Tỷ lệ tối đa & tính chất điện
| Manufacturer | Infineon Technologies |
| Series | OptiMOS 6 |
| Kiểu transitor | N-Channel MOSFET |
| Drain-Source Voltage (VDS) | 40 V |
| Continuous Drain Current (ID) at TA=25°C | 25 A |
| Continuous Drain Current (ID) at TC=25°C | 166 A |
| Power Dissipation (PD) at TA=25°C | 2.5 W |
| Power Dissipation (PD) at TC=25°C | 107 W |
| On-State Resistance (RDS(on)) typical @ VGS=10V | 2.0 mΩ |
| Hộp | PG-TTFN-9-3 (PQFN 3.3x3.3, source-down center-gate) |
| Kiểu lắp đặt | Surface Mount |
| Khoảng nhiệt độ hoạt động | -55°C to +150°C |
| Technology | OptiMOS 6, TrenchFET-class |
| Configuration | Single N-Channel, source-down |
| Trạng thái RoHS | Compliant |
| Cấp MSL | MSL1 (per JEDEC J-STD-020) |
Cấu hình chân IQE020N04LM6CGATMA1
| Chân 1 | S (Source / Sense) — Source connection (Kelvin sense pin for gate return) |
| Chân 2 | G (Gate) — Gate drive input (center pin, accessible from top side) |
| Chân 3 | S (Source) — Source pin |
| Chân 4 | S (Source) — Source pin |
| Chân 5 | S (Source) — Source pin |
| Chân 6 | S (Source) — Source pin |
| Chân 7 | S (Source) — Source pin |
| Chân 8 | S (Source) — Source pin |
| Chân 9 | S (Source) — Source pin |
| Chân PAD | Source / Thermal Pad — Exposed bottom pad - source potential, primary thermal path |
Khu vực hoạt động an toàn (DC, TA=25°C)
Ứng dụng tiêu biểu
IQE020N04LM6CGATMA1 phù hợp cho 6 Áp dụngs: 24V BLDC Motor Drive, Battery Management System (BMS) Protection, USB-PD Power Path / Load Switch, Synchronous Buck Converter (POL), 48V Mild-Hybrid DC-DC Stage, Hot-Swap / E-Fuse Controller.
24V BLDC Motor Drive
The IQE020N04LM6CGATMA1 is well-suited as the low-side or high-side switch in 24 V brushless DC motor half-bridges. Its 40 V VDS rating provides margin above 28 V automotive transients, while the 2.0 mΩ RDS(on) keeps conduction losses under 1 W at 20 A continuous drain current. The source-down PG-TTFN-9-3 package allows tight half-bridge layout with minimal source-inductance loop, which is critical for clean switching at 25–50 kHz PWM frequencies used in e-bike and power-tool drives. Pair with a gate driver such as the 6EDL04N02PRXUMA1 (Site MPN) for the high-side bootstrap supply.
Được đề xuất
Battery Management System (BMS) Protection
In lithium-ion battery packs from 1S to 10S (nominally 12 V to 36 V), the IQE020N04LM6CGATMA1 functions as a low-RDS(on) protection FET on the charge/discharge path. The 40 V VDS rating covers up to 12S packs with margin, and the 2.0 mΩ typical on-resistance minimizes voltage drop during peak discharge - critical for high-C-rate applications such as e-scooters and power tools. The source-down PQFN thermal pad enables direct heat sinking into the battery management PCB ground plane. Use with the TLE42744DV50ATMA1 LDO (Site MPN) for the BMS microcontroller supply rail.
Được đề xuất
USB-PD Power Path / Load Switch
For USB Power Delivery (USB-PD) and other 5 V to 20 V hot-swap/load-switch applications, the IQE020N04LM6CGATMA1 provides an efficient back-to-back or single-FET blocking switch. Its 40 V rating covers 20 V USB-PD EPR with margin, and the 25 A continuous current handles 100 W EPR power levels with low conduction loss. The source-down package keeps the PCB footprint compact at 3.3 × 3.3 mm while offering thermal performance comparable to larger 5 × 6 mm DFN parts. Combine with the BTS134DATMA1 (Site MPN) as an additional input protection switch.
Được đề xuất
Synchronous Buck Converter (POL)
As the low-side synchronous rectifier (SR) in 12 V-input point-of-load (POL) buck converters, the IQE020N04LM6CGATMA1 provides efficient current handling with low switching loss thanks to OptiMOS 6 technology. The 40 V VDS easily handles 12 V nominal with margin for transients, and the 166 A TC-rated pulsed current supports high di/dt transitions at 500 kHz+ switching frequencies. The source-down PQFN enables the SR FET to be placed very close to the high-side FET and inductor, minimizing the high-di/dt loop and reducing EMI.
Được đề xuất
48V Mild-Hybrid DC-DC Stage
In 48 V mild-hybrid automotive power systems, the IQE020N04LM6CGATMA1 can serve as the low-side primary switch in buck or as the SR FET in boost stages after the 12 V battery rail is generated. While the 40 V VDS limits direct use on the 48 V bus, it is ideal for the secondary-side 12 V conversion stage where efficiency at 20 A+ is critical. The 2.0 mΩ RDS(on) keeps total stage efficiency above 97%, and AEC-Q-style reliability from Infineon supports automotive qualification flows when paired with the IRF7815TRPBF (Site MPN).
Được đề xuất
Hot-Swap / E-Fuse Controller
The IQE020N04LM6CGATMA1 functions as the main pass-FET in 24 V hot-swap and electronic fuse (e-fuse) controllers, providing inrush current limiting and short-circuit protection. Its 40 V rating covers 24 V industrial rails, and the 25 A continuous rating supports most server and telecom board-level power requirements. The source-down package allows the FET to be soldered directly to a large copper pour, spreading the 2.5 W typical dissipation and keeping junction temperature in check during steady-state operation. Use the BTS70081EPAXUMA1 (Site MPN) for a complete integrated high-side solution.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho IQE020N04LM6CGATMA1 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | IQE036N08NM6CGSCATMA1 | IQE004NE1LM7CGATMA1 | ISC016N08NM8ATMA1 | IPT067N20NM6ATMA1 |
|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PQFN 3.3x3.3 source-down (PG-TTFN-9-3) | PQFN 3.3x3.3 source-down (same) | PQFN 3.3x3.3 family (verify pinout) | PQFN 3.3x3.3 family | PQFN 5x6 source-down |
| Drain-Source Voltage (VDS) | 40 V | 80 V | 40 V (verify) | 80 V | 200 V |
| RDS(on) typical @ VGS=10V | 2.0 mΩ | 3.6 mΩ | 0.4 mΩ | 1.6 mΩ | 6.7 mΩ |
| Technology Generation | OptiMOS 6 | OptiMOS 6 | OptiMOS 7 | OptiMOS 8 | OptiMOS 6 |
| Package Construction | Source-down center-gate | Source-down dual-side cooled | Source-down (verify) | Source-down | Source-down |
Bảo phân biệt quan trọng
- Lowest RDS(on) in 40V OptiMOS 6 PQFN 3.3x3.3 family (vsIQE036N08NM6CGSCATMA1)
- Source-down thermal architecture (vsStandard drain-down QFN MOSFETs)
- Latest OptiMOS 6 silicon generation (vsOptiMOS 5 BSZ series)
Ghi chú thiết kế
Estimated: At VDS×ID = 20 A continuous and RDS(on) = 2.0 mΩ, conduction loss is P = I² × R = 0.8 W. The source-down PG-TTFN-9-3 package transfers this heat directly into the PCB copper pour through the exposed bottom pad. On the Infineon reference 40 × 40 × 1.5 mm FR4 board with 6 cm² copper (drain side), RthJA is approximately 50 °C/W - so a 0.8 W loss raises junction temperature by ~40 °C above 25 °C ambient. For higher currents, expand copper area and add thermal vias beneath the exposed pad.
The source-down architecture places the source on the PCB-facing side. Layout the high-current return (source) as a flooded copper plane on the top layer, stitched with multiple vias to inner ground planes. Keep the gate-drive loop (gate driver output → gate resistor → FET gate → source-sense pin → gate driver ground) area under 0.5 cm² to minimize ringing. Place the gate resistor within 5 mm of the FET gate pin to limit parasitic inductance.
Do not assume VGS(th) of 4.5 V is sufficient - drive the gate to 10 V for full RDS(on) rating. Below 6 V VGS the on-resistance can be 2-3× the specified value, doubling conduction loss. Also avoid using a single large copper pour as the only source connection - use the source-sense pin (pin 1) for the gate-driver return to prevent VGS degradation under high di/dt. Finally, verify maximum junction temperature of 150 °C against your worst-case SOA operating point.
Top-side cooling: the drain is exposed on the top of the package, enabling an attached heatsink for applications requiring >5 W dissipation. For top-side cooling, use a thermal interface material (TIM) with thermal conductivity ≥ 3 W/mK and apply 0.05 mm thick. Maintain 6 mil clearance between the heatsink and any exposed gate pad or source-sense trace to prevent shorts.
Thông tin tuân thủ
RoHS and REACH compliant per Infineon product page. Not AEC-Q100 qualified - contact Infineon for automotive-grade OptiMOS 6 variants if automotive qualification is required.
