IQE036N08NM6CGSCATMA1 - 80V 118A OptiMOS 6 N-MOSFET | Infineon
MPN: IQE036N08NM6CGSCATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.1 | $2.10 |
| 10 | $1.85 | $18.50 |
| 100 | $1.52 | $152.00 |
| 500 | $1.28 | $640.00 |
| 1,000 | $1.05 | $1,050.00 |
| 5,000 | $0.88 | $4,400.00 |
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View Datasheet →IQE036N08NM6CGSCATMA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies |
| Series | OptiMOS 6 |
| Part Status | Active |
| FET Type | N-Channel |
| Drain-Source Voltage (VDS) | 80 V |
| Continuous Drain Current (ID) at TA | 16.7 A |
| Continuous Drain Current (ID) at TC | 118 A |
| Power Dissipation (PD) at TA | 2.5 W |
| Power Dissipation (PD) at TC | 125 W |
| Mounting Type | Surface Mount |
| Package / Case | PG-WHTFN-9-1 (PQFN 3.3 x 3.3 mm) |
| Technology | Trench MOSFET (OptiMOS 6) |
| Configuration | Source Down, Center Gate, Dual-Side Cooling |
| Operating Temperature Range | -55 C to +150 C (junction, per datasheet derating curves) |
| Packing | Tape and Reel (suffix ATMA1) |
| Voltage Rating | 60 V to 100 V category (80 V nominal) |
| RoHS Status | Compliant |
IQE036N08NM6CGSCATMA1 Pin Configuration
| Pin 1 | Source (Tab) — Source connection and PCB bottom thermal pad (Source Down) |
| Pin 2 | Gate — Gate drive input (center pin) |
| Pin 3 | Drain — Drain connection (top side) |
| Pin 4 | Source (Sense) — Kelvin source sense connection |
| Pin 5 | NC — Not connected (per datasheet) |
| Pin 6 | NC — Not connected (per datasheet) |
| Pin 7 | NC — Not connected (per datasheet) |
| Pin 8 | NC — Not connected (per datasheet) |
| Pin 9 | NC — Not connected (per datasheet) |
Safe Operating Area (DC, Tcase=25C)
Typical Applications
IQE036N08NM6CGSCATMA1 is suitable for 6 applications: 48 V Telecom Point-of-Load Converters, USB Power Delivery (USB-PD) Sinks and Sources, Server and Data Centre 48 V to 12 V Intermediate Bus, Industrial Synchronous Buck and Boost Converters, Hot-Swap and ORing Controllers, Motor Drive H-Bridge and Half-Bridges.
48 V Telecom Point-of-Load Converters
The IQE036N08NM6CGSCATMA1 fits 48 V telecom point-of-load (POL) converters because its 80 V VDS rating provides safe headroom above the 48 V nominal bus plus transient spikes from hot-swap events, while the 118 A TC continuous current supports high-current POL rails feeding ASICs and FPGAs. The PG-WHTFN-9-1 Source Down Center Gate package enables top-and-bottom PCB cooling, critical at >100 W converter densities. Designers place this MOSFET as the high-side or low-side switch in a 48 V to 5 V/12 V buck stage; the OptiMOS 6 trench process minimises switching losses at 100-300 kHz typical telecom POL frequencies.
Recommended
USB Power Delivery (USB-PD) Sinks and Sources
USB-PD 3.1 extended-power-range (EPR) sources deliver up to 28 V/36 V/48 V at 5 A, demanding synchronous buck-boost topologies that benefit from the IQE036N08NM6CGSCATMA1's 80 V VDS headroom. As a low-side synchronous rectifier, the part's low OptiMOS 6 figure of merit (RDS(on) x Qg) reduces conduction and switching losses, enabling higher charger efficiency and smaller magnetics. The 3.3 x 3.3 mm source-down footprint fits the tight PCB real estate of USB-PD wall adapters and laptop docking stations, and the central-gate layout balances gate-drive symmetry when paralleled for higher current.
Recommended
Server and Data Centre 48 V to 12 V Intermediate Bus
Hyperscale data centres increasingly adopt 48 V intermediate bus architectures (e.g. Open Compute Project standards) feeding 12 V point-of-load stages, and the IQE036N08NM6CGSCATMA1 is purpose-built for the primary-side high-current switch in these converters. The 118 A TC current rating supports multi-kilowatt converters with paralleled MOSFETs, and the dual-side cooling through top PCB copper and the exposed source pad drastically reduces junction temperature rise under full load. Compared with a TO-220 or TO-LL alternative, the source-down PQFN cuts PCB footprint by 70% while maintaining thermal performance.
Recommended
Industrial Synchronous Buck and Boost Converters
Industrial 24 V and 36 V DC bus rails (e.g. factory automation, robotic controllers, AGV batteries) require robust synchronous buck and boost stages, and the IQE036N08NM6CGSCATMA1 serves as the main switching FET or synchronous rectifier in these converters. The 80 V VDS provides safe margin over 24 V nominal plus 40% transient overshoot events common with inductive loads and motor back-EMF. The OptiMOS 6 trench technology's low Qrr reduces dead-time losses in synchronous-rectifier operation, raising converter efficiency by 0.5-1.5% versus older generations.
Recommended
Hot-Swap and ORing Controllers
The IQE036N08NM6CGSCATMA1 fits high-current 48 V hot-swap and ORing applications in telecom rectifiers and server backplanes because the 80 V VDS handles transient spikes from capacitive loads during board insertion, and the 118 A TC rating supports 100 A continuous hot-swap circuits. As the main pass-FET in a hot-swap controller, the MOSFET must survive inrush SOA events; the PG-WHTFN-9-1 source-down package spreads heat through the PCB during the brief inrush period. Compared with a D2PAK alternative, the source-down PQFN enables top-side cooling for higher power density in blade-server designs.
Recommended
Motor Drive H-Bridge and Half-Bridges
Brushless DC (BLDC) and permanent-magnet synchronous motor (PMSM) drives in 24-48 V battery-powered equipment (e-mobility, robotics, drones) use H-bridge or three-phase inverter stages where the IQE036N08NM6CGSCATMA1 serves as a low-side or high-side switch. The 80 V VDS tolerates motor back-EMF spikes, and the source-down package's thermal performance enables continuous 50-80 A phase currents without external heatsinks. The OptiMOS 6 RDS(on) versus gate-charge trade-off reduces both conduction loss (I^2 x RDS(on)) and switching loss (Qg x Vdrive x fsw), extending battery runtime in e-mobility applications.
Recommended
Recommended Products Summary
Engineering reference data for IQE036N08NM6CGSCATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ISC016N08NM8ATMA1 | IQE004NE1LM7CGATMA1 | IQDH35N03LM5CGATMA1 | IQD005N04NM6CGATMA1 |
|---|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon |
| Package | PG-WHTFN-9-1 (PQFN 3.3x3.3) | PG-WHTFN-9-1 (PQFN 3.3x3.3) - same | PG-WHTFN-9-1 (PQFN 3.3x3.3) - same | PG-WHTFN-9-1 (PQFN 3.3x3.3) - same | PG-WHTFN-9-1 (PQFN 3.3x3.3) - same |
| FET Type | N-Channel | N-Channel | N-Channel | N-Channel | N-Channel |
| Drain-Source Voltage (VDS) | 80 V | 80 V | 120 V | 30 V | 40 V |
| Continuous Drain Current at TC | 118 A | Comparable (same die family) | Lower (higher VDS variant) | Comparable | Comparable |
| Technology | OptiMOS 6 | OptiMOS 6 (newer die) | OptiMOS 7 | OptiMOS 5 | OptiMOS 6 |
| Configuration | Source Down, Center Gate, Dual-Side Cooling | Source Down, Center Gate, Dual-Side Cooling - same | Source Down, Center Gate, Dual-Side Cooling - same | Source Down, Center Gate, Dual-Side Cooling - same | Source Down, Center Gate, Dual-Side Cooling - same |
| Approx. Unit Price @ 1k (USD, as of 2026-09-14) | 1.05 | 1.25 (newer die premium) | 1.45 (higher VDS variant) | 0.95 (older OptiMOS 5) | 0.98 |
Key Differentiators
- Dual-side cooling source-down package (vs BSC0502NSIATMA1 (drain-down PQFN))
- OptiMOS 6 trench technology with best-in-class FOM (vs IQDH35N03LM5CGATMA1 (OptiMOS 5))
- Center-gate layout for balanced parallel operation (vs ISC011N06LM5ATMA1 (corner-gate PQFN))
Design Notes
The PG-WHTFN-9-1 Source Down Center Gate Dual-Side Cooling package extracts heat through both the top-side drain pad and the bottom-side source tab, enabling significantly lower junction-to-ambient thermal resistance compared with conventional drain-down PQFN footprints. Designers should place copper pours on both top and bottom PCB layers directly under the part, and use thermal vias to stitch them. Estimated: at 80 V VDS and 118 A TC, sustained conduction loss of I^2 x RDS(on) can exceed 30 W in worst-case load; adequate copper area and airflow are required to keep Tj below 125 C.
The center-gate layout of the IQE036N08NM6CGSCATMA1 minimises gate-loop parasitic inductance, which is critical for high-frequency switching (200 kHz-1 MHz) where ringing can exceed the gate-drive absolute maximum rating. Use a Kelvin source connection from the gate-driver ground to the source-sense pin rather than the power-source tab to avoid ground-bounce induced gate-drive errors. Per the Infineon OptiMOS 6 layout guidelines, place the gate-driver within 5 mm of the gate pin and use a 4-layer PCB with a dedicated ground plane under the power stage.
Estimate: keep the high-side and low-side MOSFETs in a half-bridge layout with mirror symmetry so the power-loop inductance is minimised; a typical target for 48 V POL converters is below 2 nH total loop inductance. Place the input decoupling capacitors as close as possible between the drain of the high-side FET and the source of the low-side FET. The Source Down package lets the high-current source return path flow directly through the bottom-side copper, which significantly reduces loop inductance versus conventional drain-down layouts.
Do not operate the IQE036N08NM6CGSCATMA1 continuously at the 118 A TC rating without verifying the actual case temperature stays within the SOA curves, as the datasheet reference TC is 25 C and real designs derate to 100-125 C. Also, ensure Vgs stays within +/-20 V absolute maximum; a gate-drive supply of 10-12 V with negative turn-off of -3 V to -5 V is recommended to prevent parasitic turn-on in half-bridge configurations. Finally, verify the breakdown voltage during inductive switching transients (load-dump, motor back-EMF) does not exceed 80 V; consider a TVS clamp or snubber for motor-drive applications.
Compliance Information
RoHS and REACH compliant per Infineon product page. Not AEC-Q100 qualified; for automotive designs choose the Infineon IAUC100N08S5N043ATMA1 or equivalent automotive-grade variant.
