IPT059N15N3ATMA1 - 150V 5.9mΩ 155A OptiMOS 3 Power MOSFET | Infineon
Référence : IPT059N15N3ATMA1 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $4.12 | $4,12 |
| 10 | $3.68 | $36,80 |
| 100 | $3.21 | $321,00 |
| 500 | $2.74 | $1 370,00 |
| 1 000 | $2.38 | $2 380,00 |
| 3 000 | $2.05 | $6 150,00 |
IPT059N15N3ATMA1 Présentation
A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled three-terminal switch used to route and modulate current in power-conversion circuits. Within the broader semiconductor hierarchy, the MOSFET sits inside the discrete-semiconductors > transistors > MOSFETs family, and the IPT059N15N3 belongs specifically to the sub-100 V-to-150 V high-current OptiMOS 3 generation that bridges standard 100 V logic-level FETs and 200 V+ high-voltage devices. The TOLL (TO-Leadless) package is a PCB-footprint-compatible evolution of the D²PAK (TO-263) family, offering smaller area and lower package inductance (~1 nH) for switching frequencies above 100 kHz.
Key features include 5.9 mΩ maximum RDS(on) at VGS = 10 V, a logic-level-compatible 10 V gate drive, an integrated gate-protection Zener clamp, and a thermally efficient top-side cooling pad. The low gate charge (Qg typically 90 nC) and low Qgd reduce driver losses in hard-switched topologies, while the 150 V VDS rating provides 30 % design margin above a 100 V nominal rail.
Internally, OptiMOS 3 uses Infineon's strip-cell trench layout that maximises channel width per die area, lowering both RDS(on) and Qg*Rg figure-of-merit. The result is a part that is simultaneously low-loss in conduction and fast in switching, making it well-suited to high-current synchronous rectification and motor-drive applications.
Typical applications include 48 V forklift and light-electric-vehicle motor drives, telecom point-of-load (POL) converters, eMobility battery disconnect switches, hot-swap controllers, and high-current DC-DC buck stages. The TOLL footprint suits high-density PCB designs where D²PAK would consume too much area.
Design consideration: at 155 A continuous, PCB copper spreading and via arrays under the source tab are critical; the TOLL package's low thermal resistance only helps if the board is designed as a heatsink. For maximum SOA, keep junction temperature below 150 °C and use a 10 V VGS drive with a gate-source resistor in the 10–47 Ω range to control ringing.
This page synthesises distributor pricing, drop-in alternative MPNs, and practical TOLL-layout notes not consolidated in the Infineon datasheet.
Alternatives de remplacement direct pour IPT059N15N3ATMA1 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec IPT059N15N3ATMA1 (même facteur de forme et même empreinte) — différant par Technology, Package, Mounting Type, Operating Temperature Range, Drain-Source Voltage (VDS).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
IPP075N15N3GXKSA1
✅ Remplacement direct✓ En stock
$1.92 / unité
Voir la fiche technique →BSC076N04NDATMA1
✅ Remplacement direct✓ En stock
$0.82 / unité
Voir la fiche technique →IPD50N06S409ATMA2
✅ Remplacement direct✓ En stock
$0.49 / unité
Voir la fiche technique →ISC015N06NM5ATMA1
✅ Remplacement direct✓ En stock
$0.62 / unité
Voir la fiche technique →IAUC120N06S5L015ATMA1
✅ Remplacement direct✓ En stock
$0.92 / unité
Voir la fiche technique →IPT059N15N3ATMA1 Valeurs maximales et caractéristiques électriques
| Type de transistor | N-Channel MOSFET |
| Technology | OptiMOS™ 3 (trench) |
| Drain-Source Voltage (VDS) max | 150 V |
| Continuous Drain Current (ID) at TC=25°C | 155 A |
| Static Drain-Source On-Resistance RDS(on) max @ VGS=10V | 5.9 mΩ |
| Power Dissipation (PD) at TC=25°C | 375 W |
| Gate-Source Voltage (VGS) max | ±20 V |
| Boîtier | PG-HSOF-8-1 (TOLL / TO-Leadless) |
| Type de montage | Surface Mount |
| Plage de température de fonctionnement | -55 °C to +175 °C (TJ max 175 °C) |
| Nombre de broches | 8 + exposed source tab |
| Statut RoHS | Compliant |
| Niveau MSL | 1 |
| Automotive Qualified | No (industrial grade; non-AEC-Q) |
Configuration des broches de IPT059N15N3ATMA1
| Broche 1 | G — Gate |
| Broche 2 | S — Source (electrically common with exposed tab) |
| Broche 3 | S — Source |
| Broche 4 | S — Source |
| Broche 5 | S — Source |
| Broche 6 | S — Source |
| Broche 7 | S — Source |
| Broche 8 | D — Drain |
| Broche TAB | S — Exposed metal tab = Source (also thermal pad) |
Zone de fonctionnement sûr (DC, T_C=25°C)
Applications typiques
IPT059N15N3ATMA1 convient pour 6 applications: 48 V Forklift and LEV Motor Drive, Telecom 48 V Point-of-Load DC-DC Converter, Hot-Swap and ORing Controllers, Solar Inverter / Battery Disconnect Switch, High-Current Synchronous Buck Stage, Industrial Welding and Plasma Cut Power.
48 V Forklift and LEV Motor Drive
The IPT059N15N3ATMA1 is purpose-built for 48 V forklift and light-electric-vehicle traction drives, where its 150 V VDS handles the worst-case 58 V battery plus regen transient (~70 V) with safety margin. Its 5.9 mΩ max RDS(on) at VGS=10 V keeps conduction loss below 0.91 W at 50 A, directly extending drive range per battery charge. The TOLL package's exposed source tab enables top-side liquid or forced-air cooling inside the motor-controller housing, while the low package inductance (~1 nH) supports PWM frequencies up to 50 kHz without severe ringing. Compared with a D²PAK alternative, the IPT059N15N3 saves ~40 % PCB area, enabling more compact inverter modules.
Recommandé
Telecom 48 V Point-of-Load DC-DC Converter
In 48 V telecom point-of-load (POL) converters stepping down to 12 V or 5 V, the IPT059N15N3ATMA1 serves as the synchronous-rectifier low-side FET. Its 5.9 mΩ RDS(on) keeps rectifier loss under 0.5 % of throughput, while the 150 V rating is comfortable margin above the 60 V worst-case transient on a 48 V bus. The OptiMOS 3 trench technology delivers low Qg (~90 nC) and Qgd so the gate-driver can switch at 200–500 kHz, shrinking magnetics. The TOLL footprint fits in 1/8-brick and 1/16-brick modules where D²PAK would exceed the board area budget, and the exposed tab provides the thermal path to the chassis baseplate.
Recommandé
Hot-Swap and ORing Controllers
The IPT059N15N3ATMA1 is well-suited as the main pass-FET in 48 V server and telecom hot-swap controllers, where it must survive inrush surges of several hundred amps during board insertion. Its 155 A continuous ID and 375 W PD rating cover sustained loads, while the 150 V VDS protects against transient ring-up when the load is decoupled. The TOLL package's low RθJC enables the FET to absorb the inrush energy without tripping the thermal limit. The 5.9 mΩ RDS(on) produces only ~0.7 V drop at 120 A, keeping the upstream supply within regulation even at full server startup load. Recommended companions provide the inrush ramp and current-limit feedback loop.
Recommandé
Solar Inverter / Battery Disconnect Switch
In solar string inverters and battery energy-storage disconnect switches, the IPT059N15N3ATMA1 acts as the main isolation MOSFET rated for the DC bus up to 100 V with switching transients. Its 150 V VDS gives 50 % margin above 100 V nominal, while 5.9 mΩ RDS(on) keeps conduction loss low during continuous battery discharge cycles. The TOLL footprint's top-side cooling tab allows direct mounting to the inverter chassis, simplifying thermal design in outdoor enclosures. Compared to a relay, the FET provides silent, arc-free switching with millisecond response for fault isolation. The OptiMOS 3 technology gives repeatable on-resistance across temperature, important for accurate state-of-charge monitoring.
Recommandé
High-Current Synchronous Buck Stage
As the low-side synchronous rectifier in a 100 V-to-12 V buck converter delivering 60–100 A, the IPT059N15N3ATMA1 offers an RDS(on) so low that rectifier loss falls below 0.5 % efficiency penalty. The 150 V VDS easily supports the maximum input spec of industrial 100 V bus plus ringing, and the 155 A continuous rating allows single-FET designs up to ~80 A without paralleling. The TOLL package's 1 nH source-lead inductance keeps gate-drive ringing manageable, enabling clean switching at 200 kHz. Compared with discrete D²PAK designs, the IPT059N15N3 reduces PCB area by ~40 % and improves thermal spreading via the top tab.
Recommandé
Industrial Welding and Plasma Cut Power
Industrial welding and plasma-cut power supplies use the IPT059N15N3ATMA1 in the primary-side switching stage because its 150 V VDS and 155 A continuous ID handle the rectified mains plus choke energy. The 5.9 mΩ RDS(on) keeps conduction loss low even at the kilohertz switching rates typical of IGBT-replacement MOSFET designs, while the TOLL footprint supports the high-density PCB layout required for portable welders. The exposed source tab allows direct chassis mounting in fan-cooled enclosures. OptiMOS 3's avalanche-rated body diode gives extra margin during commutation events, increasing reliability under harsh load conditions such as arc strikes and short circuits.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour IPT059N15N3ATMA1 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | IPP075N15N3GXKSA1 | BSC076N04NDATMA1 | IPD50N06S409ATMA2 | ISC015N06NM5ATMA1 | IAUC120N06S5L015ATMA1 |
|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-HSOF-8-1 (TOLL) | TO-220 (through-hole) | PG-TDSON-8-1 (SuperSO8) — same 8-pin family | PG-TO252-3 (DPAK) | PG-TDSON-8-1 | PG-TDSON-8-1 |
| VDS max | 150 V | 150 V | 40 V | 60 V | 60 V | 60 V |
| RDS(on) max @ VGS=10V | 5.9 mΩ | 7.5 mΩ | 7.6 mΩ | 4.9 mΩ | 1.5 mΩ | 1.5 mΩ |
| Technology | OptiMOS 3 trench | OptiMOS 3 trench | OptiMOS 5 | OptiMOS 2 | OptiMOS 5 | OptiMOS 5 |
| Mounting Type | Surface Mount (TOLL) | Through-Hole (TO-220) | Surface Mount | Surface Mount (DPAK) | Surface Mount | Surface Mount |
Principaux différenciateurs
- Lowest RDS(on) in the 150 V TOLL class (vs IPP075N15N3GXKSA1 (TO-220, 7.5 mΩ))
- 150 V rating with 155 A continuous current (vs BSC076N04NDATMA1 (40 V, 50 A))
- Top-side cooling via exposed source tab (vs IPD50N06S409ATMA2 (DPAK, 50 A, 60 V))
Notes de conception
Estimated: at PD = 7 W (VIN=100 V, VOUT=12 V, IOUT=80 A sync-rect conduction loss), with TOLL RθJA ≈ 35 °C/W on a 1 oz copper 100 cm² spreader, junction temperature rises 245 °C above 25 °C ambient — exceeding 175 °C TJ max. To stay within SOA at 80 A continuous, the PCB copper spreader must be enlarged to at least 200 cm² (top tab + bottom copper) or use active cooling. The exposed source tab MUST be soldered to the thermal land with multiple thermal vias (≥ 9 × 0.3 mm) to the opposite-side copper plane for double-sided heat extraction.
Use a Kelvin-source connection for the gate-drive return path: route the gate-driver GND directly to the Source pin (pin 2) of the TOLL package, NOT to the PCB ground plane, to suppress source-inductance-induced gate ringing. Add a 10 Ω gate-series resistor and a 100 kΩ gate-source pull-down to prevent accidental turn-on during power-up. Place a 1 nF ceramic bypass (CGS) directly between Gate and Source to dampen Miller-induced glitches at the drain dv/dt transition. Estimated: package source inductance is ~1 nH; without a gate resistor, peak VGS overshoot at 50 A/200 ns switching can exceed 20 V and damage the gate oxide.
Layout the TOLL package with the drain (pin 8) and source tab forming a tight power loop of < 10 mm² perimeter to minimise parasitic inductance — high di/dt during switching will otherwise generate destructive VDS overshoot. Route the gate trace on the opposite PCB layer from the power loop, separated by a continuous GND plane. Use 2 oz copper on top and bottom layers for the source tab and drain pad to maximise current capacity and thermal spreading. Place the gate driver within 5 mm of the gate pin to limit gate-loop inductance below 5 nH.
Do NOT exceed VGS = ±20 V (gate-oxide absolute max). Most failures of TOLL-package MOSFETs in the field are caused by VGS overshoot during switching, not by VDS breakdown. Always use a gate-source Zener clamp (e.g. 12 V TVS) or a gate-driver IC with built-in clamping if the layout has high source inductance. Also avoid continuous operation above 80 % of RDS(on) max — temperature rise shifts RDS(on) by ~50 % between 25 °C and 150 °C TJ, so design with 30 % current derating for sustained loads.
For switching frequencies above 100 kHz, the IPT059N15N3ATMA1 should be paired with a gate driver having 2 A peak source/sink capability (e.g. 1EDN7116GXTMA1 or IRS2110SPBF) to drive Qg quickly. Estimated: at Qg_total = 90 nC and 2 A peak driver current, the gate-rise time is ~45 ns; if your controller's dead-time is shorter than 50 ns, add a 4.7 Ω gate-source resistor to slow the turn-on transition and limit dV/dt-induced drain-voltage ringing. For 48 V POL applications, an RC snubber (10 Ω + 1 nF) across the drain-source can further reduce ringing by 30 %.
Informations de conformité
RoHS and REACH compliant per Infineon product page; lead-free reflow soldering compatible. Not AEC-Q100 qualified — for automotive use, request the AEC-Q100 version (if released) from Infineon FAE.
