10AS066K3F35E2SG - Arria 10 SX SoC FPGA 660K LE | Altera
MPN: 10AS066K3F35E2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3812.9 | $3,812.90 |
| 10 | $3685.5 | $36,855.00 |
| 100 | $3420 | $342,000.00 |
| 500 | $3185 | $1,592,500.00 |
| 1,000 | $2950 | $2,950,000.00 |
Drop-in alternatives for 10AS066K3F35E2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS066K3F35E2LG
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$2310 / Unit
View Datasheet →10AS066K2F35E2SG
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$2890 / Unit
View Datasheet →10AS066K2F35E2LG
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$3360 / Unit
View Datasheet →10AS066K2F35I2SG
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$5750 / Unit
View Datasheet →10AS066K1F35E1HG
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View Datasheet →10AS066K3F35I2SG
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$3405 / Unit
View Datasheet →10AS066K3F35E2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Device | 10AS066 |
| Logic Elements | 660K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Process Node | 20 nm |
| Package | 1152-ball FCBGA (35x35 mm) |
| Maximum User I/O | 396 |
| Speed Grade | 3 |
| Operating Temperature Grade | E (Extended) |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount (FCBGA) |
10AS066K3F35E2SG 1152-ball fcbga (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS066K3F35E2SG (1152-ball fcbga (35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K3F35E2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K3F35E2SG is suitable for 6 applications: Software Defined Radio Baseband, Industrial Motor Control and Robotics, Medical Imaging Accelerators, Broadcast Video Processing, Test and Measurement Instrumentation, Aerospace and Defense Signal Intelligence.
Software Defined Radio Baseband
The 10AS066K3F35E2SG fits SDR baseband processing because its dual ARM Cortex-A9 HPS can run a Linux/RTOS network stack and supervisory control while the 660K-logic-element FPGA fabric executes deterministic FFT, channelization, and demodulation pipelines in parallel. The integrated HPS eliminates the latency and board-area penalty of a separate companion processor, and at 1.5 GHz the A9 cores provide enough headroom for upper-MAC and protocol-handling tasks. Compared with a discrete CPU + FPGA approach, designers save a board, reduce pin count, and simplify clock-domain crossing. Verified to support typical 4G/5G PHY sub-framer workloads in production radio platforms.
Recommended
Industrial Motor Control and Robotics
In industrial servo and multi-axis robot controllers the 10AS066K3F35E2SG's combination of 660K LE FPGA fabric and a deterministic ARM Cortex-A9 HPS lets engineers implement high-rate current/torque control loops in hardware while running trajectory planning and EtherCAT/CAN-FD stacks on the HPS. The extended (E) temperature grade supports factory-floor environments. Real-time interrupt latency from the FPGA fabric to the HPS via the AXI bridge is typically sub-microsecond, well within the closed-loop period of modern servo drives at 32 kHz PWM. The 1152-FCBGA package and high pin count (396 user I/O) accommodate the many encoder, resolver, and gate-driver interfaces of multi-axis systems.
Recommended
Medical Imaging Accelerators
Ultrasound beamformers and CT image-reconstruction pipelines benefit from the 10AS066K3F35E2SG's parallel DSP and on-chip memory bandwidth, while the Cortex-A9 HPS handles the user interface, DICOM networking, and patient-data management. The deterministic ARM cores are suitable for IEC 62304 software lifecycle processes required in medical devices. Hardware-accelerated FIR filtering, FFT-based Doppler processing, and back-projection kernels map efficiently onto the FPGA fabric, leaving the HPS free for application-layer software. Single-chip integration simplifies IEC 60601-1 EMI/EMC compliance by reducing external interconnect.
Recommended
Broadcast Video Processing
For 4K/UHD broadcast routers, multiviewers, and IP-to-SDI gateway products the 10AS066K3F35E2SG provides enough logic and DSP to handle multi-channel HEVC/H.264 encode or decode at broadcast frame rates, with the dual Cortex-A9 HPS running control-plane software, NMOS IS-04/IS-05 discovery, and redundant stream management. SMPTE ST 2110 IP-based video flows can be processed directly on-chip via the integrated transceivers, eliminating external NIC silicon. The 660K LE budget accommodates multi-channel HDR/WCG conversion pipelines in parallel.
Recommended
Test and Measurement Instrumentation
High-end oscilloscopes, logic analyzers, and protocol testers leverage the 10AS066K3F35E2SG's parallel fabric for waveform capture, triggering, and protocol decoding while the Cortex-A9 HPS hosts the UI, file system, and remote control (LXI, SCPI). Deterministic FPGA-side processing supports deep memory acquisition without jitter, and the rich HPS peripherals (USB, Ethernet, PCIe) simplify instrument I/O. The 396 user I/O pins accommodate high-channel-count logic analyzer probes and mixed-signal front-ends. Single-chip integration reduces instrument cost and improves MTBF.
Recommended
Aerospace and Defense Signal Intelligence
The 10AS066K3F35E2SG's hardened ARM Cortex-A9 HPS plus 660K LE FPGA fabric suit EW, SIGINT, and radar front-end processing platforms where both cryptographic/security processing and high-rate DSP are required on the same board. Single-chip integration reduces SWaP-C (size, weight, power, and cost) on airborne platforms. Designers can partition classification/encryption workloads onto the HPS running a security-hardened OS while DSP and pulse-compression run on the FPGA. The extended (E) temperature grade supports avionics bay environments; for harsher profiles, I-temp ordering codes are available within the same package.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K3F35E2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K3F35E2LG | 10AS066K2F35E2SG | 10AS066K2F35E2LG | 10AS066K2F35I2SG | 10AS066K1F35E1HG | 10AS066K3F35I2SG |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 1152-FCBGA (35x35 mm) | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same |
| Logic Elements | 660K | 660K | 660K | 660K | 660K | 660K | 660K |
| Speed Grade | 3 | 3 | 2 | 2 | 2 | 1 | 3 |
| Temperature Grade | E (Extended) | I (Industrial) | E (Extended) | I (Industrial) | E (Extended) | H (Hot) | E (Extended) |
| HPS Cores | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| HPS Clock Speed | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Process Node | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| Approx. Unit Price (USD, qty 1) | $3,812.90 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Speed grade 3 (fastest bin in the 10AS066 K-series) (vs 10AS066K2F35E2SG)
- Extended (E) temperature grade for industrial environments (vs 10AS066K3F35I2SG)
- Single-chip SoC integration of dual ARM Cortex-A9 + 660K LE (vs Discrete CPU + separate FPGA approach)
- Rich hardened IP blocks reduce soft-logic overhead (vs Earlier-generation SoC FPGAs (Cyclone V SoC))
Design Notes
The 1152-ball FCBGA (F35, 35x35 mm) package requires a microvia/HDI PCB stack-up to fan out the dense ball grid. Designers should plan for at least a 1-2-1 or 2-2-2 build-up structure with via-in-pad for the inner rows, controlled-impedance routing for transceiver lanes (typically 85 ohm differential), and matched-length tuning for DDR3/4 interfaces to the HPS. Verify stack-up early with the Altera Arria 10 F35 package footprint and land pattern recommendations.
At full transceiver utilization and high DSP toggle rates, the 10AS066K3F35E2SG can dissipate 15-25 W typical and require active thermal management. Mount the FCBGA onto a high-performance thermal interface material with a heatsink or top-side cold plate. Estimated: theta_JA of the FCBGA package on a JEDEC 8-layer test board is roughly 8-12 C/W without airflow, implying junction temperature rise of 120-300 C at 15-25 W - clearly above the 100 C junction limit without forced airflow.
The 10AS066K3F35E2SG requires multiple supply rails: VCC (core), VCCP (periphery), VCC_HPS, VCC_HPS_IO, transceiver supplies, and auxiliary rails. Each rail has strict sequencing requirements per the Arria 10 family datasheet. Use PMBus-controlled point-of-load regulators with the Intel-recommended power-tree reference design. Decoupling must include 0.1 uF X7R near each power pin and bulk capacitors per the pin connection guidelines. Inrush current during configuration can exceed 4 A and must be considered in the upstream converter design.
Common pitfalls include: (1) omitting the external configuration flash (EPCQ) bitstream, causing the FPGA to fail on every cold boot; (2) neglecting HPS boot-mode strap pins, locking the device out of SD or QSPI boot; (3) ignoring transceiver reference-clock jitter, which can degrade multi-gigabit link margin; (4) using non-Intel-qualified DDR3/4 memory parts without running the Quartus memory IP calibration; (5) failing to apply the latest Arria 10 errata sheet updates before tape-out. Always run Quartus fitter with the device-specific pin assignments and review the Pin Connection Guidelines document.
Compliance Information
RoHS compliant per Altera/Intel product page. The SG suffix typically denotes lead-free finish. AEC-Q100 not applicable as this is a high-density FPGA/SoC, not an automotive-grade qualified IC.
