10AS066H3F34I2SG - Arria 10 SX SoC FPGA 660K LE | Intel | 1152-FBGA
MPN: 10AS066H3F34I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4199.6711 | $4,199.67 |
| 10 | $3950 | $39,500.00 |
| 100 | $3700 | $370,000.00 |
| 500 | $3450 | $1,725,000.00 |
| 1,000 | $3200 | $3,200,000.00 |
Drop-in alternatives for 10AS066H3F34I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS066H3F34I2LG
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View Datasheet →10AS066H3F34E2SG
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$3600 / Unit
View Datasheet →10AS066H2F34I2SG
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$3550 / Unit
View Datasheet →10AS066H2F34I2LG
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$11050 / Unit
View Datasheet →10AS066H2F34E2SG
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$2400 / Unit
View Datasheet →10AS066H1F34I1HG
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$3720 / Unit
View Datasheet →10AS066H1F34E1HG
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$3900 / Unit
View Datasheet →10AS066H3F34I2SG Maximum Ratings & Electrical Characteristics
| Device Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 |
| Process Node | 20 nm |
| Hard Processor System | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Core Frequency | 1.5 GHz |
| User I/O Count | 492 |
| Package | 1152-FBGA, FC (F34) 35x35 mm |
| Supply Voltage | 0.9 V core |
| Temperature Grade | Industrial |
| Operating Temperature | -40C to +100C |
| Mounting Type | Surface Mount (BGA) |
| Memory Controllers | Hard DDR3/DDR4 controller in HPS and FPGA fabric |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS066H3F34I2SG 1152-fbga, fc (f34) 35x35 mm Pin Configuration Guide
Complete pinout information for 10AS066H3F34I2SG (1152-fbga, fc (f34) 35x35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066H3F34I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066H3F34I2SG is suitable for 6 applications: Wireless Baseband Processing, Broadcast Video Encoder/Transcoder, Military Radar and Electronic Warfare, Medical Imaging Pre-Processing, Industrial Machine Vision, Embedded Compute Platform (HPS-centric).
Wireless Baseband Processing
The 10AS066H3F34I2SG is well suited for LTE and 5G small-cell baseband processing because its 660K logic elements and H3-grade transceivers support multi-antenna MIMO datapaths and high-rate CPRI/OBSAI links. With 1.5 GHz dual-core Cortex-A9 HPS, designers can host the PHY control plane on Linux/RTOS while implementing time‑critical DSP blocks in FPGA fabric. The 492 user I/O and hardened PCIe Gen3 blocks ease fronthaul connectivity to baseband cards.
Recommended
Broadcast Video Encoder/Transcoder
Broadcast video encoders benefit from the 10AS066H3F34I2SG's combination of high logic density for HEVC/H.264 pipeline blocks and a 1.5 GHz Cortex-A9 subsystem for transport-stream muxing and IP control. The H3 transceiver rate enables uncompressed 3G-SDI and SMPTE 2022-6/2110 IP video ingest over 10 Gigabit Ethernet. Industrial temperature grade supports outside-broadcast and studio equipment racks without extra thermal screening.
Recommended
Military Radar and Electronic Warfare
Phased-array radar and electronic-warfare subsystems leverage the 10AS066H3F34I2SG's combination of 660K logic elements, hardened DSP blocks, and multi-gigabit transceivers to process wideband I/Q data from ADC arrays. The Cortex-A9 HPS runs the real-time task scheduler while FPGA fabric handles FFT, pulse compression, and beamforming in deterministic hardware. The F34 1152-ball FCBGA provides the I/O density required for many ADC/DAC lanes on a single board.
Recommended
Medical Imaging Pre-Processing
Ultrasound and CT imaging pre-processing pipelines map naturally onto the 10AS066H3F34I2SG's parallel fabric. Beamforming, FIR filtering, and image reconstruction accelerate on the programmable logic, while the Cortex-A9 HPS handles the user interface, DICOM stack, and post-processing. The industrial temperature rating and lead-free F34 package meet medical device compliance requirements, and the 492 user I/O accommodate high-channel-count ADC front ends.
Recommended
Industrial Machine Vision
High-speed production-line inspection systems use the 10AS066H3F34I2SG to process multi-camera 10 GigE Vision streams in parallel FPGA pipelines. The dual-core Cortex-A9 HPS runs the vision application's decision logic, while the FPGA fabric performs Bayer demosaicing, defect detection, and 25 Gbps uplink aggregation. The F34 FCBGA's high ball count allows multi-channel sensor fan-in without external aggregation ASICs.
Recommended
Embedded Compute Platform (HPS-centric)
Designers building control-plane plus data-plane products can use the 10AS066H3F34I2SG as a Linux/RTOS host with FPGA accelerators. The Cortex-A9 MPCore runs the application stack, while FPGA fabric offloads packet processing, cryptography, or DSP. The 1152-ball F34 FCBGA provides the I/O and transceiver bandwidth needed for industrial Ethernet, PCIe Gen3, and high-speed memory interfaces on a single board.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066H3F34I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066H3F34I2LG | 10AS066H3F34E2SG | 10AS066H2F34I2SG | 10AS066H2F34I2LG | 10AS066H2F34E2SG | 10AS066H1F34I1HG |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1152-FBGA, FC (F34) 35x35 mm | 1152-FBGA, FC (F34) 35x35 mm - same | 1152-FBGA, FC (F34) 35x35 mm - same | 1152-FBGA, FC (F34) 35x35 mm - same | 1152-FBGA, FC (F34) 35x35 mm - same | 1152-FBGA, FC (F34) 35x35 mm - same | 1152-FBGA, FC (F34) 35x35 mm - same |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 |
| Transceiver Speed Grade | H3 | H3 | H3 | H2 | H2 | H2 | H1 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Enhanced (-40C to +125C) | Industrial | Industrial | Enhanced | Industrial |
| HPS Cores | Dual-core ARM Cortex-A9 @ 1.5 GHz | Dual-core ARM Cortex-A9 @ 1.5 GHz | Dual-core ARM Cortex-A9 @ 1.5 GHz | Dual-core ARM Cortex-A9 @ 1.5 GHz | Dual-core ARM Cortex-A9 @ 1.5 GHz | Dual-core ARM Cortex-A9 @ 1.5 GHz | Dual-core ARM Cortex-A9 @ 1.5 GHz |
| User I/O Count | 492 | 492 | 492 | 492 | 492 | 492 | 492 |
| RoHS Compliance | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Key Differentiators
- Highest transceiver speed grade (H3) in the 10AS066 family (vs 10AS066H2F34I2SG)
- Industrial temperature grade (-40C to +100C) with H3 transceivers (vs 10AS066H3F34E2SG)
- 660K logic elements and 492 user I/O on a 20 nm Arria 10 SX die (vs 10AS032E3F27I2SG)
Design Notes
The 1152-ball F34 FCBGA (35x35 mm) demands a high-layer-count PCB (typically 12+ layers) with microvia stackups and matched-length routing for transceiver lanes. Place decoupling capacitors as close to each power ball group as the breakout allows, with separate VCC, VCCPT, VCCA_FPLL, and VCC_HPS rails routed as wide pours. Reference Intel's Arria 10 SX F34 pin-out file and recommended decoupling guideline in Quartus Prime before finalizing stackup.
Estimated: at typical SoC FPGA power of 20-30 W for the 10AS066 with high transceiver utilization, the F34 package requires a heat sink and 200-400 LFM airflow to stay within the 100C industrial junction limit. Use a thermal interface material rated for 3 W/mK or better and a heat spreader across the package top. Estimate: with theta_JA of approximately 1.5 C/W with a typical heat sink at 200 LFM, 25 W dissipation yields a 37.5C rise above ambient, leaving 25C headroom under 100C ambient - sized correctly for industrial deployments.
Do not assume transceiver lanes are preconfigured - Quartus Prime assignments must match the F34 ball map and the PCB routing layer. Power-up sequencing (VCC, VCCPT, VCCA_FPLL, VCC_HPS) must follow the Intel Arria 10 power management guide; failure to sequence correctly causes latch-up. Ensure HPS boot mode strapping pins are pulled correctly for SD/eMMC/NAND boot, and that JTAG chain is properly terminated for boundary-scan and debug access.
Compliance Information
RoHS compliance per Globalspec and Partstack listings of 2026-09. Industrial-grade temperature range. Not AEC-Q100 qualified (industrial FPGAs are typically not AEC-Q100; AEC-Q100 qualification is more common on specific automotive variants).
