Intel

10AX115N1F40E1SG - Arria 10 GX FPGA, 1150K LE, 1517-FCBGA | Intel

MPN: 10AX115N1F40E1SG ✓ Active

In Stock Ships in 1-3 business days

1517-BBGA, FCBGA (F40) Package -E1 (fastest) Speed 68,857,856 bits Memory

From $6995 USD / Unit

MOQ: 1 |

Price updated: 2026-09-04

Volume Pricing

Qty	Unit Price	Extended
1	$8450	$8,450.00
10	$8120	$81,200.00
100	$7650	$765,000.00
500	$7280	$3,640,000.00
1,000	$6995	$6,995,000.00

ℹ️ All prices are in USD

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10AX115N1F40E1SG Overview

The Intel 10AX115N1F40E1SG is a high-density Arria 10 GX Field-Programmable Gate Array (FPGA) delivering 1,150,000 logic elements, 68,857,856 bits of embedded memory, and 600 user I/O pins in a 1517-ball FCBGA package. It belongs to the -E1 (fastest) speed grade in Intel's 20nm Arria 10 family and targets mid- to high-end FPGA-based designs in communications, broadcast, and signal-processing systems.

What is an FPGA? A Field-Programmable Gate Array is a class of programmable logic device containing an array of configurable logic blocks (CLBs), programmable interconnect, and hardened IP blocks such as transceivers, memory controllers, and DSP slices. FPGAs sit within the broader semiconductor hierarchy: programmable logic -> logic device -> integrated circuit -> semiconductor. They offer hardware-level parallelism and the ability to reconfigure logic post-deployment, making them ideal for evolving standards, custom data-path acceleration, and time-to-market-critical designs where ASIC NRE costs are prohibitive.

Key features include integrated 28.05 Gbps transceivers supporting backplanes and chip-to-chip links, hardware DSP blocks delivering up to 1.5 TFLOPS of fixed/floating-point throughput, hard memory controllers for DDR4 and DDR3, and PCI Express Gen3 x8 hard IP. The device also integrates dual ARM Cortex-A9 MPCore hard processors for system-on-chip designs. The 1517-FCBGA package uses a 1.0mm ball pitch and supports extended-temperature operation.

Architecturally, the Arria 10 GX combines a 20nm tri-gate process with hard floating-point multipliers in DSP blocks, eliminating soft-logic multipliers to reduce power and latency. Its Adaptive Logic Module (ALM) packs eight inputs with two combinational outputs and two register outputs, doubling logic density vs. older 6-input LUT architectures. This translates into lower power per DSP operation and more deterministic timing closure.

Typical applications include 100G/400G Ethernet line cards, military radar signal processing, medical imaging accelerator boards, professional video broadcast (4K/8K UHD), and high-performance computing (HPC) test infrastructure. The combination of 28G transceivers and PCIe Gen3 makes it well suited for data-acquisition front ends.

When designing with this device, plan power delivery for the core (0.9V/0.95V), I/O banks (1.2V-3.3V), and transceiver rails separately, and validate thermal envelopes using the Quartus PowerPlay early power estimator before PCB commitment. Use the F40 package variant when migrating between speed grades within the same footprint.

This page synthesizes distributor pricing, drop-in pin-compatible alternatives drawn from the same Arria 10 family, and practical design notes not consolidated in the manufacturer datasheet.

Drop-in alternatives for 10AX115N1F40E1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with 10AX115N1F40E1SG (same form factor and footprint) — differing in Package, Speed Grade, DSP Blocks, Operating Temperature, Embedded Memory Bits.

10AX115N1F40I1SG

Intel

Package: 1517-ball FC-FBGA (F40)

Speed Grade: 1

DSP Blocks: Variable-precision hardened DSP