10CX105YF780I6G - Cyclone 10 GX FPGA 104K LE | Intel | 780-FBGA
MPN: 10CX105YF780I6G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1826.62 | $1,826.62 |
| 10 | $1750 | $17,500.00 |
| 100 | $1620 | $162,000.00 |
| 250 | $1555 | $388,750.00 |
| 500 | $1495 | $747,500.00 |
Drop-in alternatives for 10CX105YF780I6G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10CX105YF780E6G
✅ Drop-In✓ In Stock
$580 / Unit
View Datasheet →10CX105YF780I5G
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →10CX105YF780E5G
✅ Drop-In✓ In Stock
$350 / Unit
View Datasheet →10CX150YF780I6G
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$325 / Unit
View Datasheet →10CX220YF780I6G
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$121.83 / Unit
View Datasheet →10CX105YF780I6G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 GX |
| Logic Elements | 104,000 |
| Embedded Memory (bits) | 8,641,536 |
| Adaptive Logic Modules (ALMs) | 39,360 |
| Embedded 18x18 Multipliers | 156 |
| Transceiver Channels | 6 (up to 6.144 Gbps) |
| User I/O Pins | 284 |
| PCIe Hard IP | 1 Gen2 (x4) hard block |
| Memory Controllers (Hard) | 2 (DDR3/DDR4/LPDDR3) |
| PLLs | 4 (one per side) |
| Process Technology | 20 nm |
| Package | 780-Ball FCBGA |
| Temperature Grade | Industrial (-40C to +100C) |
| Speed Grade | 6 |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| MSL Level | 3 (168 hours) |
10CX105YF780I6G Pin Configuration
| Pin 1 | VCC — Core supply pin (1.0 V typical) |
| Pin 2 | GND — Ground reference |
| Pin 3 | I/O — General-purpose user I/O bank 1A |
| Pin 4 | I/O — General-purpose user I/O bank 1A |
| Pin 5 | I/O — General-purpose user I/O bank 1B |
| Pin 6 | I/O — General-purpose user I/O bank 1B |
| Pin 7 | I/O — General-purpose user I/O bank 2A |
| Pin 8 | I/O — General-purpose user I/O bank 2A |
| Pin 9 | I/O — General-purpose user I/O bank 2B |
| Pin 10 | I/O — General-purpose user I/O bank 2B |
| Pin 11 | I/O — General-purpose user I/O bank 3A |
| Pin 12 | I/O — General-purpose user I/O bank 3A |
| Pin 13 | I/O — General-purpose user I/O bank 3B |
| Pin 14 | I/O — General-purpose user I/O bank 3B |
| Pin 15 | I/O — General-purpose user I/O bank 4A |
| Pin 16 | I/O — General-purpose user I/O bank 4A |
| Pin 17 | I/O — General-purpose user I/O bank 4B |
| Pin 18 | I/O — General-purpose user I/O bank 4B |
| Pin 19 | I/O — General-purpose user I/O bank 5A |
| Pin 20 | I/O — General-purpose user I/O bank 5A |
| Pin 21 | I/O — General-purpose user I/O bank 5B |
| Pin 22 | I/O — General-purpose user I/O bank 5B |
| Pin 23 | I/O — General-purpose user I/O bank 6A |
| Pin 24 | I/O — General-purpose user I/O bank 6A |
| Pin 25 | I/O — General-purpose user I/O bank 6B |
| Pin 26 | I/O — General-purpose user I/O bank 6B |
| Pin 27 | I/O — General-purpose user I/O bank 7A |
| Pin 28 | I/O — General-purpose user I/O bank 7A |
| Pin 29 | I/O — General-purpose user I/O bank 7B |
| Pin 30 | I/O — General-purpose user I/O bank 7B |
| Pin 31 | I/O — General-purpose user I/O bank 8A |
| Pin 32 | I/O — General-purpose user I/O bank 8A |
| Pin 33 | I/O — General-purpose user I/O bank 8B |
| Pin 34 | I/O — General-purpose user I/O bank 8B |
| Pin 35 | I/O — General-purpose user I/O bank 9A |
| Pin 36 | I/O — General-purpose user I/O bank 9A |
| Pin 37 | I/O — General-purpose user I/O bank 9B |
| Pin 38 | I/O — General-purpose user I/O bank 9B |
| Pin 39 | I/O — General-purpose user I/O bank 10A |
| Pin 40 | I/O — General-purpose user I/O bank 10A |
| Pin 41 | I/O — General-purpose user I/O bank 10B |
| Pin 42 | I/O — General-purpose user I/O bank 10B |
| Pin 43 | I/O — General-purpose user I/O bank 11A |
| Pin 44 | I/O — General-purpose user I/O bank 11A |
| Pin 45 | I/O — General-purpose user I/O bank 11B |
| Pin 46 | I/O — General-purpose user I/O bank 11B |
| Pin 47 | I/O — General-purpose user I/O bank 12A |
| Pin 48 | I/O — General-purpose user I/O bank 12A |
| Pin 49 | I/O — General-purpose user I/O bank 12B |
| Pin 50 | I/O — General-purpose user I/O bank 12B |
| Pin 51 | I/O — General-purpose user I/O bank 13A |
| Pin 52 | I/O — General-purpose user I/O bank 13A |
| Pin 53 | I/O — General-purpose user I/O bank 13B |
| Pin 54 | I/O — General-purpose user I/O bank 13B |
| Pin 55 | I/O — General-purpose user I/O bank 14A |
| Pin 56 | I/O — General-purpose user I/O bank 14A |
| Pin 57 | I/O — General-purpose user I/O bank 14B |
| Pin 58 | I/O — General-purpose user I/O bank 14B |
| Pin 59 | I/O — General-purpose user I/O bank 15A |
| Pin 60 | I/O — General-purpose user I/O bank 15A |
| Pin 61 | I/O — General-purpose user I/O bank 15B |
| Pin 62 | I/O — General-purpose user I/O bank 15B |
| Pin 63 | I/O — General-purpose user I/O bank 16A |
| Pin 64 | I/O — General-purpose user I/O bank 16A |
| Pin 65 | I/O — General-purpose user I/O bank 16B |
| Pin 66 | I/O — General-purpose user I/O bank 16B |
| Pin 67 | I/O — High-speed transceiver reference clock input |
| Pin 68 | I/O — High-speed transceiver reference clock input |
| Pin 69 | I/O — High-speed transceiver reference clock input |
| Pin 70 | I/O — High-speed transceiver reference clock input |
| Pin 71 | REFCLK — Dedicated transceiver reference clock input |
| Pin 72 | REFCLK — Dedicated transceiver reference clock input |
| Pin 73 | I/O — Transceiver channel 0 TX/RX |
| Pin 74 | I/O — Transceiver channel 0 TX/RX |
| Pin 75 | I/O — Transceiver channel 1 TX/RX |
| Pin 76 | I/O — Transceiver channel 1 TX/RX |
| Pin 77 | I/O — Transceiver channel 2 TX/RX |
| Pin 78 | I/O — Transceiver channel 2 TX/RX |
| Pin 79 | I/O — Transceiver channel 3 TX/RX |
| Pin 80 | I/O — Transceiver channel 3 TX/RX |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX105YF780I6G is suitable for 7 applications: Industrial Machine Vision over CoaXPress, Broadcast Video Contribution Encoders, PCI Express Gen2 Endpoint Cards, Software-Defined Radio Front-Ends, Industrial Motor Drives and Servo Controllers, Medical Imaging Diagnostic Equipment, Aerospace Avionics Networking Bridges.
Industrial Machine Vision over CoaXPress
The 10CX105YF780I6G is well suited for industrial machine-vision cameras and frame grabbers because it integrates 6 hardened transceiver channels operating up to 6.144 Gbps, which directly handle CoaXPress 1.0 (up to 6.25 Gbps per lane) and 10 GigE Vision links without an external PHY. The 156 embedded 18x18 DSP blocks support real-time image pre-processing - Bayer demosaicing, lens distortion correction, and ROI cropping - in hardware, while the 8.6 Mbit embedded M20K memory buffers several scanlines of high-resolution image data. Compared with the Cyclone 10 LP family, only the 10CX105 adds the hard transceiver and PCIe Gen2 blocks needed for these protocols.
Recommended
Broadcast Video Contribution Encoders
The 10CX105YF780I6G suits broadcast contribution encoders (SMPTE 2022-6, SMPTE 2110 over 10 GbE) because its transceivers carry uncompressed SDI over 10GBASE-R, while the 104K logic elements run JPEG-XS, NDI, or H.264 encoders in soft logic. The 2 hard memory controllers route up to DDR4-1600 to on-chip buffers at 25.6 Gbps, enough for 4K60 4:2:2 video. Designers choose the 10CX105 over the 10CL120 because the LX family lacks the transceiver channels required for SDI over fiber or 10 GbE.
Recommended
PCI Express Gen2 Endpoint Cards
The 10CX105YF780I6G is a strong fit for low-density PCIe Gen2 endpoint cards (data-acquisition, software-defined radio, industrial I/O) because it integrates a hardened PCIe Gen2 x4 controller, removing the soft-logic overhead and timing closure headaches of a SERDES-based PCIe soft implementation. The 284 user I/Os plus 8.6 Mbit of on-chip memory handle moderate DMA buffers and protocol state machines. Designers step up to the 10CX220 only when they need additional FPGA fabric for multi-lane protocol bridging.
Recommended
Software-Defined Radio Front-Ends
The 10CX105YF780I6G serves SDR front-end processing boards because the 6 transceivers deliver up to 6.144 Gbps of raw IQ data from external ADC/DAC front-ends (e.g., the Analog Devices AD9361 or AD9371), while the 156 DSP blocks implement digital down-conversion, channelization, and pulse shaping at line rate. The Industrial -40C/+100C temperature range covers ground-mobile and avionics SDR enclosures. The 10CX105 has more fabric and transceivers than the Cyclone V equivalent 5CEFA7 (149.5K LEs but only 6 transceivers at 3.125 Gbps), making it the better fit for wideband SDR.
Recommended
Industrial Motor Drives and Servo Controllers
The 10CX105YF780I6G fits high-end industrial motor drives and multi-axis servo controllers because it integrates enough DSP blocks (156 18x18 multipliers) to implement field-oriented control (FOC) loops on 4 to 6 axes simultaneously, plus transceivers for encoder feedback (EnDat 2.2, BISS, SSI over RS-422) and EtherCAT slave connectivity. The industrial temperature grade supports factory-floor ambient conditions. The 8.6 Mbit embedded memory holds reference trajectories and per-axis state without external SRAM.
Recommended
Medical Imaging Diagnostic Equipment
The 10CX105YF780I6G suits portable and bedside medical imaging diagnostic equipment (ultrasound beamformers, endoscopy video processors, dermatology scanners) because the hardened transceivers carry ultrasound RF data at multi-Gbps line rate, while the DSP blocks implement beamforming and image reconstruction in real time. The 2 hard memory controllers route high-resolution image data to DDR4. Engineers choose the 10CX105 over the 10CX220 because the additional density of the 220 part would be wasted, and over the 10CX085 because the additional 2 transceiver channels simplify multi-probe designs.
Recommended
Aerospace Avionics Networking Bridges
The 10CX105YF780I6G is used in aerospace avionics networking bridges and protocol converters (ARINC 429, MIL-STD-1553, ARINC 664 / AFDX) because the 6 transceivers provide redundant ARINC 664 channels while the 104K logic elements run multi-protocol translation state machines with margin for safety wrappers (DO-254 DAL-B/DAL-C). Industrial temperature grade and BGA package robustness match avionics bay requirements. For DAL-A designs, the 10CL120YF780I7G logic-only companion handles the simpler fault-isolated sections at lower cost.
Recommended
Recommended Products Summary
Engineering reference data for 10CX105YF780I6G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX105YF780E6G | 10CX105YF780I5G | 10CX105YF780E5G | 10CX150YF780I6G | 10CX220YF780I6G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 780-FCBGA | 780-FCBGA - same | 780-FCBGA - same | 780-FCBGA - same | 780-FCBGA - same | 780-FCBGA - same |
| Logic Elements | 104,000 | 104,000 (same) | 104,000 (same) | 104,000 (same) | 150,000 (+44%) | 220,000 (+112%) |
| Embedded Memory (Mbit) | 8.6 | 8.6 (same) | 8.6 (same) | 8.6 (same) | 12.5 (+45%) | 18.4 (+114%) |
| Transceiver Channels | 6 | 6 (same) | 6 (same) | 6 (same) | 12 (+100%) | 12 (+100%) |
| Max Transceiver Data Rate (Gbps) | 6.144 | 6.144 (same) | 6.144 (same) | 6.144 (same) | 6.144 (same) | 6.144 (same) |
| User I/O Pins | 284 | 284 (same) | 284 (same) | 284 (same) | 284 (same) | 284 (same) |
| Speed Grade | 6 | 6 (same) | 5 (slower) | 5 (slower) | 6 (same) | 6 (same) |
| Temperature Grade | Industrial (-40C to +100C) | Extended (0C to +85C) | Industrial (-40C to +100C) | Extended (0C to +85C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) |
| PCIe Hard IP | 1x Gen2 x4 | 1x Gen2 x4 | 1x Gen2 x4 | 1x Gen2 x4 | 1x Gen2 x4 | 2x Gen2 x4 |
Key Differentiators
- Mid-density position with hardened 6-channel transceiver block (vs 10CX085 (same family, lower density))
- Lower cost than the 10CX150 while retaining 6.144 Gbps transceiver data rate (vs 10CX150YF780I6G (same family, higher density))
- Industrial temperature grade at no cost premium versus extended grade (vs 10CX105YF780E6G (Extended temp variant))
Design Notes
The 10CX105YF780I6G requires four independent supply rails: VCC (1.0 V core, ~2-3 A typical, transient to 5 A during power-up), VCCAUX (2.5 V for PLLs and configuration, ~150 mA), VCCA_FPLL (1.8 V for transceiver PLL, ~50 mA), and VCCIO (1.2-3.3 V I/O bank-dependent). Power sequencing must follow the Intel Cyclone 10 GX device family datasheet: VCC ramp first, then VCCAUX within 100 ms, then VCCIO and VCCA_FPLL. Reverse-voltage protection on each rail is recommended. Estimated: total in-rush energy can peak at 15-20 mJ if all banks switch simultaneously.
The 780-FCBGA package has a thermal resistance (theta_JB) of approximately 0.5 C/W and (theta_JC) of 0.1 C/W per Intel packaging thermal models. Without thermal management, junction temperature can exceed 100 C with just 3 W of dissipation. Use a 4-layer PCB minimum with 2 inner copper ground planes stitched to the BGA ground balls; for designs approaching 5 W, add a top-side heatsink or a 25 x 25 mm copper heat-spreader. Estimated: at 4 W dissipation, expect a 50 C junction rise on a JEDEC-standard 4-layer board.
The 780-FCBGA has 1.0 mm ball pitch and requires microvia PCB fabrication (HDI stack-up: 1-n-1 or 2-n-2). Each BGA pad needs a via-in-pad with filled and plated-over construction, plus a 0.5 mm pad-to-pad keep-out for breakout routing. Use a 50 ohm controlled-impedance stack-up (typically 8 layers total: signal/GND/signal/GND/PWR/signal/GND/signal) for transceiver channels. Reference the Cyclone 10 GX PCB design guidelines for length-matching, decoupling capacitor placement, and routing topology. Estimated: minimum PCB fabrication cost is approximately 30% higher than non-HDI boards.
The 6 transceiver channels of the 10CX105YF780I6G operate at up to 6.144 Gbps, which requires careful signal-integrity management. Use continuous reference ground planes directly beneath each transceiver route, never split a ground plane under a channel, and avoid crossing layers. AC-coupling capacitors (100 nF) are required on each transmit and receive differential pair; place them within 50 mm of the FPGA balls. Reference clock lines require 100 ohm differential impedance and length matching within 0.5 mm.
Three common pitfalls to avoid: (1) Do not enable the hard PCIe Gen2 block if your design does not use PCIe; unused transceiver channels should be powered down and tri-stated to reduce EMI. (2) Do not omit the external 100 MHz PCIe reference clock; the on-chip PLL cannot generate PCIe compliance frequencies. (3) Do not exceed 5,000 program/erase cycles on the configuration flash; use the Cyclone 10 GX partial reconfiguration capability for firmware updates instead of full reconfiguration.
Compliance Information
RoHS and REACH compliant per Intel product page; AEC-Q100 not applicable as this is an FPGA not an automotive IC. Halogen-free status not explicitly stated in the verified web data.
